The Week Of Monday 22 April 2024 Archives by date
Starting: Mon Apr 22 00:00:42 PDT 2024
Ending: Sun Apr 28 23:55:45 PDT 2024
Messages: 4925
- [llvm] [MIPS]: Rework atomic max/min expand for subword (PR #89575)
YunQiang Su via llvm-commits
- [llvm] [MIPS]: Rework atomic max/min expand for subword (PR #89575)
via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Jay Foad via llvm-commits
- [llvm] [MIPS]: Rework atomic max/min expand for subword (PR #89575)
YunQiang Su via llvm-commits
- [llvm] [MIPS]: Rework atomic max/min expand for subword (PR #89575)
YunQiang Su via llvm-commits
- [llvm] [MIPS] Sign-extend subwords when expanding atomic max/min (PR #89246)
YunQiang Su via llvm-commits
- [llvm] [Inline][Cloning] Defer constant propagation after phi-nodes resolution (PR #87963)
Antonio Frighetto via llvm-commits
- [llvm] [MIPS]: Rework atomic max/min expand for subword (PR #89575)
YunQiang Su via llvm-commits
- [llvm] [MIPS] Sign-extend subwords when expanding atomic max/min (PR #89246)
YunQiang Su via llvm-commits
- [llvm] [PAC][MC][AArch64] Fix error message for AUTH_ABS64 reloc with ILP32 (PR #89563)
Daniil Kovalev via llvm-commits
- [llvm] [ValueTracking] Compute knownbits from known fp classes (PR #86409)
Yingwei Zheng via llvm-commits
- [llvm] [AArch64] Replace AND with LSL#2 for LDR target (#34101) (PR #89531)
via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Simon Pilgrim via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Simon Pilgrim via llvm-commits
- [llvm] [ValueTracking] Compute knownbits from known fp classes (PR #86409)
Yingwei Zheng via llvm-commits
- [llvm] Fix uninitialized variable (PR #89040)
Malay Sanghi via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Xu Zhang via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU-specific module splitting (PR #89245)
Pierre van Houtryve via llvm-commits
- [llvm] [CodeGen] Tail Duplication: Remove irrelevant phi node workaround (PR #86981)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Xu Zhang via llvm-commits
- [llvm] [docs] Document which online sync-ups are no longer happening (PR #89361)
Kristof Beyls via llvm-commits
- [llvm] [docs] Document which online sync-ups are no longer happening (PR #89361)
Simon Moll via llvm-commits
- [llvm] d18ab0e - [InstCombine] Fold fabs over selects (#86390)
via llvm-commits
- [llvm] [InstCombine] Fold fabs over selects (PR #86390)
Yingwei Zheng via llvm-commits
- [llvm] [Inline][Cloning] Defer constant propagation after phi-nodes resolution (PR #87963)
Antonio Frighetto via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
David Green via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
David Green via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
David Green via llvm-commits
- [llvm] [docs] Document which online sync-ups are no longer happening (PR #89361)
Michal Paszkowski via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
David Green via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU-specific module splitting (PR #89245)
Pierre van Houtryve via llvm-commits
- [llvm] 83f7a3a - [llvm-split] Require x86-registered-target for target-specific-split.ll
via llvm-commits
- [llvm] [SelectionDAG] Remove redundant KnownBits smin and smax operations (PR #89519)
Matt Arsenault via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
David Green via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
David Green via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
David Green via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
David Green via llvm-commits
- [llvm] a4bacb0 - [SelectionDAG] Remove redundant KnownBits smin and smax operations (#89519)
via llvm-commits
- [llvm] [SelectionDAG] Remove redundant KnownBits smin and smax operations (PR #89519)
Matt Arsenault via llvm-commits
- [llvm] [DAGCombine] Transform `shl X, cttz(Y)` to `mul (Y & -Y), X` if cttz is unsupported (PR #85066)
Yingwei Zheng via llvm-commits
- [llvm] [mlir] [mlir][python] Fix generation of Python bindings for `async` dialect (PR #75960)
Oleksandr Alex Zinenko via llvm-commits
- [llvm] 7f975b6 - [AArch64] Add tests for more undef lanes on zip/uzp. NFC
David Green via llvm-commits
- [llvm] Fix uninitialized variable (PR #89040)
Isha Agarwal via llvm-commits
- [llvm] Fix uninitialized variable (PR #89040)
Isha Agarwal via llvm-commits
- [llvm] [RISCV] Defer forming x0, x0 vsetvlis until after insertion (PR #89089)
Luke Lau via llvm-commits
- [llvm] [RISCV] Defer forming x0, x0 vsetvlis until after insertion (PR #89089)
Luke Lau via llvm-commits
- [llvm] [RISCV] Defer forming x0, x0 vsetvlis until after insertion (PR #89089)
Luke Lau via llvm-commits
- [llvm] [MemCpyOpt] Continue merging memset with unrelated clobber (PR #89550)
Yingwei Zheng via llvm-commits
- [llvm] 3fbaad5 - [VectorCombine] Add test coverage for #89390
Simon Pilgrim via llvm-commits
- [llvm] 4cc9c6d - [VectorCombine] foldShuffleOfBinops - don't fold shuffle(divrem(x,y),divrem(z,w)) if mask contains poison
Simon Pilgrim via llvm-commits
- [llvm] [InstCombine] Fold fcmp into select (PR #86482)
Matt Arsenault via llvm-commits
- [llvm] [DAGCombine] Transform `shl X, cttz(Y)` to `mul (Y & -Y), X` if cttz is unsupported (PR #85066)
Matt Arsenault via llvm-commits
- [llvm] [Nomination] New Intel representative for the security group (PR #89435)
Peter Smith via llvm-commits
- [llvm] [LTO] Allow target-specific module splittting (PR #83128)
Yingwei Zheng via llvm-commits
- [llvm] [AArch64] Match ZIP and UZP starting from undef elements. NFC (PR #89578)
David Green via llvm-commits
- [llvm] [AArch64] Match ZIP and UZP starting from undef elements. NFC (PR #89578)
via llvm-commits
- [llvm] [RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Luke Lau via llvm-commits
- [llvm] [RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Luke Lau via llvm-commits
- [llvm] [RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Luke Lau via llvm-commits
- [llvm] dc9664a - CodeGen: Strengthen definition of F{MIN|MAX}NUM_IEEE nodes (#85195)
via llvm-commits
- [llvm] CodeGen: Strengthen definition of F{MIN|MAX}NUM_IEEE nodes (PR #85195)
Matt Arsenault via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
Simon Pilgrim via llvm-commits
- [llvm] [Linker] Propagate `nobuiltin` attributes when linking known libcalls (PR #89431)
Guillaume Chatelet via llvm-commits
- [llvm] adb2547 - [llvm-split] Add missing TargetParser dependency
via llvm-commits
- [llvm] [LTO] Allow target-specific module splittting (PR #83128)
Pierre van Houtryve via llvm-commits
- [llvm] [WIP][RFC] Teach MCA constant registers do not create dependencies (PR #89387)
Rin Dobrescu via llvm-commits
- [llvm] [SelectionDAG] Treat CopyFromReg as freezing the value (PR #85932)
Yingwei Zheng via llvm-commits
- [llvm] [InstCombine] Fold fcmp into select (PR #86482)
Yingwei Zheng via llvm-commits
- [clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)
via llvm-commits
- [clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)
via llvm-commits
- [llvm] [ValueTracking] Compute knownbits from known fp classes (PR #86409)
Matt Arsenault via llvm-commits
- [llvm] [LTO] Allow target-specific module splittting (PR #83128)
Yingwei Zheng via llvm-commits
- [llvm] [InstCombine] Fold fcmp into select (PR #86482)
Yingwei Zheng via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
Simon Pilgrim via llvm-commits
- [llvm] [RISCV] Re-model RVV comparison instructions (PR #88868)
Luke Lau via llvm-commits
- [clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)
Yingwei Zheng via llvm-commits
- [compiler-rt] [llvm] [RISCV][sanitizer] Fix sanitizer support for different virtual memory layout (PR #66743)
Hau Hsu via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
Peter Waller via llvm-commits
- [llvm] [bazel] Add a bazel flag to enable building MLIR with CUDA support (PR #88856)
Adam Paszke via llvm-commits
- [llvm] [TBAA] Add verifier for tbaa.struct metadata (PR #86709)
Julian Nagele via llvm-commits
- [llvm] RenameIndependentSubregs: Add missing sub-range for new IMPLICIT_DEFs (PR #89050)
Matt Arsenault via llvm-commits
- [llvm] RenameIndependentSubregs: Add missing sub-range for new IMPLICIT_DEFs (PR #89050)
Matt Arsenault via llvm-commits
- [llvm] [TBAA] Add verifier for tbaa.struct metadata (PR #86709)
Christian Ulmann via llvm-commits
- [llvm] [NFC][RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Piyou Chen via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
YunQiang Su via llvm-commits
- [llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
Xu Zhang via llvm-commits
- [llvm] [Passes] opt Segmentation fault with the pass "codegenprepare" (PR #89566)
via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
Peter Waller via llvm-commits
- [llvm] [X86][AVX] Prefer per-element vector shifts for known splats #39424 (PR #87913)
via llvm-commits
- [llvm] [AArch64][GlobalISel] Combine Shuffles of G_CONCAT_VECTORS (PR #87489)
via llvm-commits
- [llvm] [llvm-readobj] Remove --raw-relr (PR #89426)
James Henderson via llvm-commits
- [llvm] [AArch64] Match ZIP and UZP starting from undef elements. NFC (PR #89578)
Sam Tebbs via llvm-commits
- [llvm] [LV] Calculating explicit vector length using vector trip count (PR #89580)
Mel Chen via llvm-commits
- [llvm] [LV] Calculating explicit vector length using vector trip count (PR #89580)
via llvm-commits
- [llvm] [InstCombine] Canonicalise SextADD + GEP (PR #69581)
Bruno De Fraine via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
YunQiang Su via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] [ARM] r11 is reserved when using -mframe-chain=aapcs (PR #86951)
via llvm-commits
- [llvm] c88b84d - [DAG] visitOR/visitORLike - merge repeated SDLoc calls.
Simon Pilgrim via llvm-commits
- [clang] [clang-tools-extra] [compiler-rt] [flang] [libc] [libclc] [libcxx] [libcxxabi] [libunwind] [lld] [lldb] [llvm] [mlir] [openmp] [polly] [pstl] Update IDE Folders (PR #89153)
Michael Kruse via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Matt Arsenault via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] AMDGPU: Add description for new atomicrmw metadata (PR #85052)
Matt Arsenault via llvm-commits
- [llvm] ca9a44e - [DAG] visitORCommutative - use sd_match to reduce the need for commutative operand matching. NFCI.
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG]: Have isKnownNeverZero treat SRL like division if all else fails (PR #89523)
Jay Foad via llvm-commits
- [llvm] 821935b - [AArch64][GlobalISel] Combine Shuffles of G_CONCAT_VECTORS (#87489)
via llvm-commits
- [llvm] [AArch64][GlobalISel] Combine Shuffles of G_CONCAT_VECTORS (PR #87489)
via llvm-commits
- [llvm] [LV] Calculating explicit vector length using vector trip count (PR #89580)
Florian Hahn via llvm-commits
- [llvm] [LV] Calculating explicit vector length using vector trip count (PR #89580)
Florian Hahn via llvm-commits
- [llvm] [LV] Calculating explicit vector length using vector trip count (PR #89580)
Florian Hahn via llvm-commits
- [llvm] c8e5ad4 - Revert "[TBAA] Add verifier for tbaa.struct metadata (#86709)"
Florian Hahn via llvm-commits
- [llvm] [RISCV] Re-model RVV comparison instructions (PR #88868)
Pengcheng Wang via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
David Spickett via llvm-commits
- [llvm] [bazel] Add a bazel flag to enable building MLIR with CUDA support (PR #88856)
Christian Sigg via llvm-commits
- [llvm] [TBAA] Add verifier for tbaa.struct metadata (PR #86709)
Florian Hahn via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
Martin Storsjö via llvm-commits
- [llvm] [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (PR #88295)
Luke Lau via llvm-commits
- [llvm] [MemCpyOpt] Continue merging memset with unrelated clobber (PR #89550)
via llvm-commits
- [llvm] [X86] Allow input vector extracted from larger vector when combining to VPMADDUBSW (PR #89584)
Phoebe Wang via llvm-commits
- [llvm] [X86] Allow input vector extracted from larger vector when combining to VPMADDUBSW (PR #89584)
via llvm-commits
- [llvm] [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (PR #88295)
Luke Lau via llvm-commits
- [llvm] Add an all-in-one histogram intrinsic, along with lowering for AArch64 (PR #88106)
Sam Tebbs via llvm-commits
- [llvm] [KnownBitsTest] Common up isCorrect and isOptimal. NFC. (PR #89585)
Jay Foad via llvm-commits
- [llvm] [bazel] Add a bazel flag to enable building MLIR with CUDA support (PR #88856)
Adam Paszke via llvm-commits
- [llvm] [KnownBitsTest] Common up isCorrect and isOptimal. NFC. (PR #89585)
via llvm-commits
- [llvm] [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (PR #88295)
Luke Lau via llvm-commits
- [llvm] Add an all-in-one histogram intrinsic, along with lowering for AArch64 (PR #88106)
Matt Arsenault via llvm-commits
- [llvm] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (PR #89069)
Jeremy Morse via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
Simon Pilgrim via llvm-commits
- [llvm] [KnownBitsTest] Common up isCorrect and isOptimal. NFC. (PR #89585)
Jay Foad via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
Peter Waller via llvm-commits
- [llvm] AMDGPU: Simplify DS atomicrmw fadd handling (PR #89468)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Refactor atomicrmw fadd expansion logic (PR #89469)
Pierre van Houtryve via llvm-commits
- [llvm] [NVPTX] Add support for atomic add for bf16 type (PR #89586)
Adrian Kuegel via llvm-commits
- [llvm] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (PR #89069)
Florian Hahn via llvm-commits
- [llvm] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (PR #89069)
Florian Hahn via llvm-commits
- [llvm] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (PR #89069)
Florian Hahn via llvm-commits
- [llvm] 5b6db43 - AMDGPU: Simplify DS atomicrmw fadd handling (#89468)
via llvm-commits
- [llvm] AMDGPU: Simplify DS atomicrmw fadd handling (PR #89468)
Matt Arsenault via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Matt Arsenault via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Matt Arsenault via llvm-commits
- [llvm] [ValueTracking] isNonZero trunc of sub of ptr2int's with recursive GEP where pointers are limited to a 32bit alloc. (PR #84933)
via llvm-commits
- [llvm] AMDGPU: Refactor atomicrmw fadd expansion logic (NFC) (PR #89469)
Matt Arsenault via llvm-commits
- [llvm] [KnownBitsTest] Print name of function when exhaustive tests fail (PR #89588)
Jay Foad via llvm-commits
- [llvm] [KnownBitsTest] Print name of function when exhaustive tests fail (PR #89588)
Jay Foad via llvm-commits
- [llvm] [KnownBitsTest] Print name of function when exhaustive tests fail (PR #89588)
via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
Orlando Cazalet-Hyams via llvm-commits
- [llvm] [KnownBitsTest] Print name of function when exhaustive tests fail (PR #89588)
via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
via llvm-commits
- [compiler-rt] [libcxx] CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (PR #89234)
Martin Storsjö via llvm-commits
- [llvm] AMDGPU: Refactor atomicrmw fadd expansion logic (NFC) (PR #89469)
Matt Arsenault via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
Orlando Cazalet-Hyams via llvm-commits
- [clang] [clang-tools-extra] [compiler-rt] [flang] [libc] [libclc] [libcxx] [libcxxabi] [libunwind] [lld] [lldb] [llvm] [mlir] [openmp] [polly] [pstl] Update IDE Folders (PR #89153)
Michael Kruse via llvm-commits
- [lld] [lld][ELF][AArch64] Support `R_AARCH64_GOT_LD_PREL19` relocation (PR #89592)
Daniil Kovalev via llvm-commits
- [lld] [lld][ELF][AArch64] Support `R_AARCH64_GOT_LD_PREL19` relocation (PR #89592)
Daniil Kovalev via llvm-commits
- [lld] [lld][ELF][AArch64] Support `R_AARCH64_GOT_LD_PREL19` relocation (PR #89592)
Daniil Kovalev via llvm-commits
- [lld] [lld][ELF][AArch64] Support `R_AARCH64_GOT_LD_PREL19` relocation (PR #89592)
via llvm-commits
- [llvm] [KnownBitsTest] Print name of function when exhaustive tests fail (PR #89588)
Simon Pilgrim via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
Michael Buch via llvm-commits
- [llvm] [ARM][AArch64] Split processor and feature definitions out of the ARM.td/AArch64.td [NFC] (PR #88282)
Tomas Matheson via llvm-commits
- [llvm] b7db392 - Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (#89589)
via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
Orlando Cazalet-Hyams via llvm-commits
- [llvm] Fix DW_TAG_template_alias refs in llvm-dwarfdump --verify (PR #89589)
Orlando Cazalet-Hyams via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [clang] [llvm] [mlir] [OpenMP] Migrate GPU Reductions CodeGen from Clang to OMPIRBuilder (PR #80343)
Akash Banerjee via llvm-commits
- [llvm] [ARM][AArch64] Split processor and feature definitions out of the ARM.td/AArch64.td [NFC] (PR #88282)
Tomas Matheson via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] Add foldShuffleToIdentity (PR #88693)
Alexey Bataev via llvm-commits
- [llvm] a2692ac - [llvm-split] Correctly deallocate TargetMachine
via llvm-commits
- [llvm] [KnownBitsTest] Common up isCorrect and isOptimal. NFC. (PR #89585)
Nikita Popov via llvm-commits
- [llvm] AMDGPU: fix isSafeToSink expecting exactly one predecessor (PR #89224)
Petar Avramovic via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (PR #88899)
Alexey Bataev via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Alexey Bataev via llvm-commits
- [llvm] [KnownBitsTest] Common up isCorrect and isOptimal. NFC. (PR #89585)
Simon Pilgrim via llvm-commits
- [llvm] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (PR #89069)
via llvm-commits
- [llvm] [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (PR #88743)
Simon Pilgrim via llvm-commits
- [llvm] [RISCV] Re-model RVV comparison instructions (PR #88868)
Luke Lau via llvm-commits
- [llvm] [AArch64][SME] Remove unused ZA lazy-save (PR #81648)
Sander de Smalen via llvm-commits
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Jeff Niu via llvm-commits
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Abhina Sree via llvm-commits
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Abhina Sree via llvm-commits
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Arthur Eubanks via llvm-commits
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Luke Lau via llvm-commits
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Luke Lau via llvm-commits
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Luke Lau via llvm-commits
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Orlando Cazalet-Hyams via llvm-commits
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Orlando Cazalet-Hyams via llvm-commits
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Orlando Cazalet-Hyams via llvm-commits
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Troy Butler via llvm-commits
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Yingwei Zheng via llvm-commits
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zhijian lin via llvm-commits
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Luke Lau via llvm-commits
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Luke Lau via llvm-commits
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Michael Kruse via llvm-commits
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Yingwei Zheng via llvm-commits
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Michael Maitland via llvm-commits
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Michael Maitland via llvm-commits
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Matt Arsenault via llvm-commits
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Dinar Temirbulatov via llvm-commits
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Dinar Temirbulatov via llvm-commits
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Dinar Temirbulatov via llvm-commits
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Dinar Temirbulatov via llvm-commits
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Carlos Alberto Enciso via llvm-commits
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Michael Kruse via llvm-commits
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Dinar Temirbulatov via llvm-commits
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Alex Bradbury via llvm-commits
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Orlando Cazalet-Hyams via llvm-commits
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Orlando Cazalet-Hyams via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
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Michael Maitland via llvm-commits
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Christian Sigg via llvm-commits
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Dimitry Andric via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
- [llvm] [RISCV] Add Sched classes for vector crypto instructions (PR #90068)
Craig Topper via llvm-commits
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Antonio Frighetto via llvm-commits
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Owen Anderson via llvm-commits
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Owen Anderson via llvm-commits
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Owen Anderson via llvm-commits
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Shilei Tian via llvm-commits
- [llvm] [AMDGPU][ISel] Set trunc store action to expand for v4f32->v4bf16 (PR #90427)
via llvm-commits
- [llvm] [RISCV] Generate RISCVISAInfo in JSON format from RISCVFeatures.td. (PR #90426)
Jessica Clarke via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Pengcheng Wang via llvm-commits
- [llvm] 53cda4c - [Transforms] Use LLVMContext::MD_loop (NFC)
Kazu Hirata via llvm-commits
- [llvm] [RISCV] Generate RISCVISAInfo in JSON format from RISCVFeatures.td. (PR #90426)
Jerry Zhang Jian via llvm-commits
- [llvm] [InstCombine] Fold `trunc nuw (x xor y) to i1` to `x != y` (PR #90408)
via llvm-commits
- [llvm] [AMDGPU][ISel] Set trunc store action to expand for v4f32->v4bf16 (PR #90427)
Changpeng Fang via llvm-commits
- [llvm] GlobalOpt: Handle threadlocal.address intrinsic (PR #88454)
Nikita Popov via llvm-commits
- [llvm] [AMDGPU][ISel] Set trunc store action to expand for v4f32->v4bf16 (PR #90427)
Shilei Tian via llvm-commits
- [llvm] [SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (PR #84921)
Nikita Popov via llvm-commits
- [llvm] [AMDGPU][ISel] Set trunc store action to expand for v4f32->v4bf16 (PR #90427)
Shilei Tian via llvm-commits
- [llvm] Reenable JumpTableToSwitch pass by default (PR #83229)
Nikita Popov via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [llvm] [InstCombine] Fold Minimum over Trailing/Leading Bits Counts (PR #90402)
Nikita Popov via llvm-commits
- [llvm] [InstCombine] Fold Minimum over Trailing/Leading Bits Counts (PR #90402)
Nikita Popov via llvm-commits
- [llvm] [InstCombine] Fold Minimum over Trailing/Leading Bits Counts (PR #90402)
Nikita Popov via llvm-commits
- [llvm] [InstCombine] Fold Minimum over Trailing/Leading Bits Counts (PR #90402)
Nikita Popov via llvm-commits
- [llvm] [InstCombine] Fold Minimum over Trailing/Leading Bits Counts (PR #90402)
Nikita Popov via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [flang] [llvm] [mlir] [mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (PR #90413)
via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Craig Topper via llvm-commits
- [llvm] [RISCV] Support instruction sizes up to 176-bits in disassembler. (PR #90371)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Support instruction sizes up to 176-bits in disassembler. (PR #90371)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Support instruction sizes up to 176-bits in disassembler. (PR #90371)
Pengcheng Wang via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)
Luke Lau via llvm-commits
- [llvm] [DAG] SelectionDAG.computeKnownBits - add NSW/NUW flags support to ISD::SHL handling (PR #89877)
via llvm-commits
- [llvm] [InstCombine] Fold `trunc nuw (x xor y) to i1` to `x != y` (PR #90408)
Yingwei Zheng via llvm-commits
- [llvm] [X86] matchAddressRecursively - move ZERO_EXTEND patterns into matchIndexRecursively (PR #85081)
via llvm-commits
- [llvm] [CGP] Drop poison-generating flags after hoisting (PR #90382)
Yingwei Zheng via llvm-commits
- [llvm] Reenable JumpTableToSwitch pass by default (PR #83229)
Alexander Shaposhnikov via llvm-commits
- [llvm] [X86] matchAddressRecursively - move ZERO_EXTEND patterns into matchIndexRecursively (PR #85081)
via llvm-commits
- [llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Luke Lau via llvm-commits
- [llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Luke Lau via llvm-commits
- [llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Luke Lau via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [NewPM][CodeGen] Add `MachineFunctionAnalysis` (PR #88610)
Arthur Eubanks via llvm-commits
- [llvm] [IA]: Construct (de)interleave4 out of (de)interleave2 (PR #89276)
Hassnaa Hamdi via llvm-commits
- [llvm] [RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. (PR #90428)
Yingwei Zheng via llvm-commits
- [llvm] [IA]: Construct (de)interleave4 out of (de)interleave2 (PR #89276)
Hassnaa Hamdi via llvm-commits
- [llvm] [IA]: Construct (de)interleave4 out of (de)interleave2 (PR #89276)
Hassnaa Hamdi via llvm-commits
- [clang] [compiler-rt] [llvm] [ConstantFolding] Canonicalize constexpr GEPs to i8 (PR #89872)
Arthur Eubanks via llvm-commits
- [clang] [compiler-rt] [llvm] [ConstantFolding] Canonicalize constexpr GEPs to i8 (PR #89872)
Arthur Eubanks via llvm-commits
- [llvm] [NewPM][CodeGen] Add `MachineFunctionAnalysis` (PR #88610)
via llvm-commits
- [llvm] [NewPM][CodeGen] Add `MachineFunctionAnalysis` (PR #88610)
via llvm-commits
- [llvm] [NewPM][CodeGen] Add `MachineFunctionAnalysis` (PR #88610)
via llvm-commits
- [clang] [compiler-rt] [llvm] [ConstantFolding] Canonicalize constexpr GEPs to i8 (PR #89872)
Nikita Popov via llvm-commits
- [clang] [compiler-rt] [llvm] [ConstantFolding] Canonicalize constexpr GEPs to i8 (PR #89872)
Nikita Popov via llvm-commits
- [llvm] Fix incorrect codegen with respect to GEPs #85333 (PR #88440)
Nikita Popov via llvm-commits
- [llvm] Fix incorrect codegen with respect to GEPs #85333 (PR #88440)
Nikita Popov via llvm-commits
- [llvm] [GVNSink] Fix incorrect codegen with respect to GEPs #85333 (PR #88440)
Nikita Popov via llvm-commits
- [llvm] 501cfd5 - [X86] Use static_asserts instead of assert (NFC)
Kazu Hirata via llvm-commits
- [llvm] [DAGCombiner] Freeze maybe poison operands when folding select to logic (PR #84924)
Nikita Popov via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
YunQiang Su via llvm-commits
- [llvm] 6cd6bde - [RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from arith tests (#89886)
via llvm-commits
- [llvm] [RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from arith tests (PR #89886)
Shih-Po Hung via llvm-commits
- [llvm] [InstCombine] Fold `(icmp pred (trunc nuw/nsw X), C)` -> `(icmp pred X, (zext/sext C))` (PR #87935)
Nikita Popov via llvm-commits
- [llvm] b3c55b7 - [SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)
via llvm-commits
- [llvm] [SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (PR #84921)
Björn Pettersson via llvm-commits
- [llvm] [RISCV] Don't use MachineInstr::isIdenticalTo in hasSameAVL (PR #90431)
Luke Lau via llvm-commits
- [llvm] [RISCV] Don't use MachineInstr::isIdenticalTo in hasSameAVL (PR #90431)
via llvm-commits
- [llvm] [CodeGen] Don't allow function alignment less than the target's minimum (PR #90415)
Yingchi Long via llvm-commits
- [llvm] [CodeGen] Don't allow function alignment less than the target's minimum (PR #90415)
Yingchi Long via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
Cinhi Young via llvm-commits
- [llvm] dc7834b - [ProfileData] Use static_assert instead of assert (NFC)
Kazu Hirata via llvm-commits
- [llvm] [RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost (PR #89170)
Shih-Po Hung via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
YunQiang Su via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
Cinhi Young via llvm-commits
- [flang] [llvm] [mlir] Revert "[mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (#89998)" (PR #90250)
Christian Sigg via llvm-commits
- [llvm] [NFC] Reduce copies created of ConstantRange when getting ConstantRangeAttributes. (PR #90335)
Andreas Jonson via llvm-commits
- [llvm] [NFC] Reduce copies created of ConstantRange when getting ConstantRangeAttributes. (PR #90335)
Nikita Popov via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
Cinhi Young via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
Cinhi Young via llvm-commits
- [llvm] [AMDGPU] don't mark control-flow intrinsics as convergent (PR #90026)
Sameer Sahasrabuddhe via llvm-commits
- [llvm] [AMDGPU] don't mark control-flow intrinsics as convergent (PR #90026)
Sameer Sahasrabuddhe via llvm-commits
- [llvm] [NFC] Reduce copies created of ConstantRange when getting ConstantRangeAttributes. (PR #90335)
Andreas Jonson via llvm-commits
- [llvm] ec6c0a2 - [LoongArch] Pre-commit tests for OptWInstrs. NFC
WANG Rui via llvm-commits
- [llvm] [NFC] Reduce copies created of ConstantRange when getting ConstantRangeAttributes. (PR #90335)
Andreas Jonson via llvm-commits
- [llvm] [NFC] Reduce copies created of ConstantRange when getting ConstantRangeAttributes. (PR #90335)
Andreas Jonson via llvm-commits
- [llvm] [MIPS] Implement llvm.fminimum and llvm.fmaximum with f32/f64 (PR #89907)
YunQiang Su via llvm-commits
- [llvm] [InstCombine] Canonicalize reassoc contract fmuladd to fmul + fadd (PR #90434)
via llvm-commits
- [llvm] [InstCombine] Canonicalize reassoc contract fmuladd to fmul + fadd (PR #90434)
via llvm-commits
- [llvm] [InstCombine] Canonicalize reassoc contract fmuladd to fmul + fadd (PR #90434)
via llvm-commits
Last message date:
Sun Apr 28 23:55:45 PDT 2024
Archived on: Sun Apr 28 23:55:47 PDT 2024
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