[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 22 16:06:09 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/89684
This introduces a new file, RISCVISAUtils.cpp and moves the rest of RISCVISAInfo to the TargetParser library.
This will allow us to generate part of RISCVISAInfo.cpp using tablegen.
>From fc51e3821787f1ae8dcb344d4def0ef342ae473b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 18 Apr 2024 16:47:31 -0700
Subject: [PATCH 1/7] [RISCV][TableGen] Generate RISCVTargetParser.inc from the
new RISCVExtension tblgen information.
Instead of using RISCVISAInfo's extension information, use the
extension found in tblgen after #89326.
We still need to use RISCVISAInfo code to get the sorting rules for
the ISA string.
The ISA string we generate now is not quite the same extension we
had before. No implied extensions are included in the generate string
unless they are explicitly listed in RISCVProcessors.td. This primarily
affects Zicsr being implied by F, V implying Zve*, and Zvl*b implying a
smaller Zvl*b. All of these implication should be picked up when the
string is used by the frontend.
The benefit is that we get a more manageable ISA string for humans to
deal with.
This is a step towards generating RISCVISAInfo's extension list from
tblgen.
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 43 ++++++++++---------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 62916bd62c0119..4f840b4227e45b 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -17,34 +17,34 @@
using namespace llvm;
-using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
-
// We can generate march string from target features as what has been described
// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
// Naming Conventions'.
//
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
-static std::string getMArch(const Record &Rec) {
- std::vector<std::string> FeatureVector;
+static void printMArch(raw_ostream &OS, const Record &Rec) {
+ std::map<std::string, std::pair<unsigned, unsigned>,
+ RISCVISAInfo::ExtensionComparator>
+ Extensions;
unsigned XLen = 32;
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
StringRef FeatureName = Feature->getValueAsString("Name");
- if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
- FeatureVector.push_back((Twine("+") + FeatureName).str());
- else if (FeatureName == "64bit")
+ if (Feature->isSubClassOf("RISCVExtension")) {
+ unsigned Major = Feature->getValueAsInt("MajorVersion");
+ unsigned Minor = Feature->getValueAsInt("MinorVersion");
+ Extensions.try_emplace(FeatureName.str(), Major, Minor);
+ } else if (FeatureName == "64bit")
XLen = 64;
}
- ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
- if (!ISAInfo)
- report_fatal_error("Invalid features");
+ OS << "rv" << XLen;
- // RISCVISAInfo::toString will generate a march string with all the extensions
- // we have added to it.
- return (*ISAInfo)->toString();
+ ListSeparator LS("_");
+ for (auto const &Ext : Extensions)
+ OS << LS << Ext.first << Ext.second.first << 'p' << Ext.second.second;
}
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
@@ -54,12 +54,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
// Iterate on all definition records.
for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
- std::string MArch = Rec->getValueAsString("DefaultMarch").str();
-
- // Compute MArch from features if we don't specify it.
- if (MArch.empty())
- MArch = getMArch(*Rec);
-
bool FastScalarUnalignedAccess =
any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
@@ -75,7 +69,16 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "PROC(" << Rec->getName() << ", "
<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
+ << "{\"";
+
+ StringRef MArch = Rec->getValueAsString("DefaultMarch");
+
+ // Compute MArch from features if we don't specify it.
+ if (MArch.empty())
+ printMArch(OS, *Rec);
+ else
+ OS << MArch;
+ OS << "\"}, " << FastUnalignedAccess << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
>From 815a63b99de61b8b1fde5a8c831f63d8810134db Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 18 Apr 2024 17:10:50 -0700
Subject: [PATCH 2/7] fixup! clang-format
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 4f840b4227e45b..9862a610bab4d7 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -67,9 +67,8 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
bool FastUnalignedAccess =
FastScalarUnalignedAccess && FastVectorUnalignedAccess;
- OS << "PROC(" << Rec->getName() << ", "
- << "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"";
+ OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
+ << "\"}, {\"";
StringRef MArch = Rec->getValueAsString("DefaultMarch");
>From 378531b67272efe877689fe899dd29fdc99d7b86 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 15:17:27 -0700
Subject: [PATCH 3/7] fixup! Infer 32-bit Xlen from '32bit' feature.
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 9862a610bab4d7..d6a6e8b60c1052 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -27,7 +27,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
std::map<std::string, std::pair<unsigned, unsigned>,
RISCVISAInfo::ExtensionComparator>
Extensions;
- unsigned XLen = 32;
+ unsigned XLen = 0;
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
@@ -36,10 +36,17 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
unsigned Major = Feature->getValueAsInt("MajorVersion");
unsigned Minor = Feature->getValueAsInt("MinorVersion");
Extensions.try_emplace(FeatureName.str(), Major, Minor);
- } else if (FeatureName == "64bit")
+ } else if (FeatureName == "64bit") {
+ assert(XLen == 0 && "Already determined XLen");
XLen = 64;
+ } else if (FeatureName == "32bit") {
+ assert(XLen == 0 && "Already determined XLen");
+ XLen = 32;
+ }
}
+ assert(XLen != 0 && "Unable to determine XLen");
+
OS << "rv" << XLen;
ListSeparator LS("_");
>From df505d84b3782ac1043c78db8157264da416269f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 16:29:03 -0700
Subject: [PATCH 4/7] fixup! Add unit test
---
llvm/test/TableGen/riscv-target-def.td | 96 ++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 llvm/test/TableGen/riscv-target-def.td
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
new file mode 100644
index 00000000000000..f2ea3c6d4686a5
--- /dev/null
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -0,0 +1,96 @@
+// RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+class RISCVExtension<string name, int major, int minor, string fieldname,
+ string desc, list<SubtargetFeature> implies = [],
+ string value = "true">
+ : SubtargetFeature<name, fieldname, value, desc, implies> {
+ int MajorVersion = major;
+ int MinorVersion = minor;
+ bit Experimental = false;
+}
+
+def FeatureStdExtI
+ : RISCVExtension<"i", 2, 1, "HasStdExtI",
+ "'I' (Base Integer Instruction Set)">;
+
+def FeatureStdExtZicsr
+ : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr",
+ "'zicsr' (CSRs)">;
+
+def FeatureStdExtZifencei
+ : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei",
+ "'Zifencei' (fence.i)">;
+
+def Feature32Bit
+ : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
+def Feature64Bit
+ : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
+
+// Dummy feature that isn't an extension.
+def FeatureDummy
+ : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
+
+class RISCVProcessorModel<string n,
+ SchedMachineModel m,
+ list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = [],
+ string default_march = "">
+ : ProcessorModel<n, m, f, tunef> {
+ string DefaultMarch = default_march;
+}
+
+class RISCVTuneProcessorModel<string n,
+ SchedMachineModel m,
+ list<SubtargetFeature> tunef = [],
+ list<SubtargetFeature> f = []>
+ : ProcessorModel<n, m, f,tunef>;
+
+def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI]>;
+def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI]>;
+def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>;
+
+
+def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureDummy]>;
+def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureDummy]>;
+def ROCKET : RISCVTuneProcessorModel<"rocket",
+ NoSchedModel>;
+
+// CHECK: #ifndef PROC
+// CHECK: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)
+// CHECK: #endif
+
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
+// CHECK: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
+// CHECK: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
+// CHECK: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
+
+// CHECK: #undef PROC
+
+// CHECK: #ifndef TUNE_PROC
+// CHECK: #define TUNE_PROC(ENUM, NAME)
+// CHECK: #endif
+
+// CHECK: TUNE_PROC(GENERIC, "generic")
+// CHECK: TUNE_PROC(ROCKET, "rocket")
+
+// CHECK: #undef TUNE_PROC
>From 75d26c40c1014a1beece6f8737c0c65d60a7b198 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 20 Apr 2024 19:11:44 -0700
Subject: [PATCH 5/7] fixup! indentation
---
llvm/test/TableGen/riscv-target-def.td | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index f2ea3c6d4686a5..ab589b31192f39 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -5,7 +5,7 @@ include "llvm/Target/Target.td"
class RISCVExtension<string name, int major, int minor, string fieldname,
string desc, list<SubtargetFeature> implies = [],
string value = "true">
- : SubtargetFeature<name, fieldname, value, desc, implies> {
+ : SubtargetFeature<name, fieldname, value, desc, implies> {
int MajorVersion = major;
int MinorVersion = minor;
bit Experimental = false;
@@ -37,7 +37,7 @@ class RISCVProcessorModel<string n,
list<SubtargetFeature> f,
list<SubtargetFeature> tunef = [],
string default_march = "">
- : ProcessorModel<n, m, f, tunef> {
+ : ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
}
@@ -45,7 +45,7 @@ class RISCVTuneProcessorModel<string n,
SchedMachineModel m,
list<SubtargetFeature> tunef = [],
list<SubtargetFeature> f = []>
- : ProcessorModel<n, m, f,tunef>;
+ : ProcessorModel<n, m, f,tunef>;
def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
>From 0135a83f4608bc19302fd54bf5db31de00ff76e5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 22 Apr 2024 12:34:30 -0700
Subject: [PATCH 6/7] fixup! Use RISCVISAInfo::ExtensionVersion.
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index d6a6e8b60c1052..653e5c5fdb4219 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -24,7 +24,7 @@ using namespace llvm;
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
static void printMArch(raw_ostream &OS, const Record &Rec) {
- std::map<std::string, std::pair<unsigned, unsigned>,
+ std::map<std::string, RISCVISAInfo::ExtensionVersion,
RISCVISAInfo::ExtensionComparator>
Extensions;
unsigned XLen = 0;
@@ -35,7 +35,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
if (Feature->isSubClassOf("RISCVExtension")) {
unsigned Major = Feature->getValueAsInt("MajorVersion");
unsigned Minor = Feature->getValueAsInt("MinorVersion");
- Extensions.try_emplace(FeatureName.str(), Major, Minor);
+ Extensions[FeatureName.str()] = {Major, Minor};
} else if (FeatureName == "64bit") {
assert(XLen == 0 && "Already determined XLen");
XLen = 64;
@@ -51,7 +51,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
ListSeparator LS("_");
for (auto const &Ext : Extensions)
- OS << LS << Ext.first << Ext.second.first << 'p' << Ext.second.second;
+ OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor;
}
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
>From ee9180aff45af55797d2e97c1b65f9c35b5c8a24 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 22 Apr 2024 13:19:26 -0700
Subject: [PATCH 7/7] [RISCV] Split code that tablegen needs out of
RISCVISAInfo.
This introduces a new file, RISCVISAUtils.cpp and moves the
reset of RISCVISAInfo to the TargetParser library.
This will allow us to generate part of RISCVISAInfo.cpp using
tablegen.
---
clang/lib/Basic/Targets/RISCV.h | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 2 +-
clang/lib/Driver/Driver.cpp | 2 +-
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 2 +-
clang/lib/Driver/ToolChains/Clang.cpp | 2 +-
clang/lib/Driver/ToolChains/Flang.cpp | 2 +-
clang/lib/Driver/ToolChains/Gnu.cpp | 2 +-
clang/tools/driver/cc1_main.cpp | 2 +-
lld/ELF/Arch/RISCV.cpp | 2 +-
llvm/include/llvm/Support/RISCVISAUtils.h | 42 ++++++++
.../{Support => TargetParser}/RISCVISAInfo.h | 21 +---
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/CMakeLists.txt | 2 +-
llvm/lib/Support/RISCVISAUtils.cpp | 88 +++++++++++++++++
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
.../RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 1 -
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 +-
.../MCTargetDesc/RISCVTargetStreamer.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +-
llvm/lib/TargetParser/CMakeLists.txt | 1 +
.../RISCVISAInfo.cpp | 96 +++----------------
llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +-
llvm/unittests/Support/RISCVISAInfoTest.cpp | 74 +++++++-------
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 6 +-
24 files changed, 202 insertions(+), 159 deletions(-)
create mode 100644 llvm/include/llvm/Support/RISCVISAUtils.h
rename llvm/include/llvm/{Support => TargetParser}/RISCVISAInfo.h (86%)
create mode 100644 llvm/lib/Support/RISCVISAUtils.cpp
rename llvm/lib/{Support => TargetParser}/RISCVISAInfo.cpp (93%)
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 78580b5b1c1063..9fa42e75bbfd14 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -16,7 +16,7 @@
#include "clang/Basic/TargetInfo.h"
#include "clang/Basic/TargetOptions.h"
#include "llvm/Support/Compiler.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"
#include <optional>
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 0c447b20cef40d..d085e735ecb443 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -68,9 +68,9 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ConvertUTF.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/Support/xxhash.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include <optional>
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 0da92001e08c27..76b7b9fdfb4f9b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -87,12 +87,12 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/Process.h"
#include "llvm/Support/Program.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/Regex.h"
#include "llvm/Support/StringSaver.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include <cstdlib> // ::getenv
#include <map>
#include <memory>
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 96b3cc3bb8ffb1..2e2bce8494672f 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -15,9 +15,9 @@
#include "clang/Driver/Options.h"
#include "llvm/Option/ArgList.h"
#include "llvm/Support/Error.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
using namespace clang::driver;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index f8a81ee8ab56bc..e43da1e78d9ef5 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -54,11 +54,11 @@
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/Process.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/YAMLParser.h"
#include "llvm/TargetParser/ARMTargetParserCommon.h"
#include "llvm/TargetParser/Host.h"
#include "llvm/TargetParser/LoongArchTargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include <cctype>
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp
index abe0b931676005..6d93c1f3d7034a 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -15,7 +15,7 @@
#include "llvm/Frontend/Debug/Options.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include <cassert>
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
index dedbfac6cb25d2..f55b8bf48c13f7 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,8 +30,8 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/TargetParser.h"
#include <system_error>
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index b5c6be3c557bb3..2aebc6d3c01782 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -39,7 +39,6 @@
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/Process.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/Signals.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/TimeProfiler.h"
@@ -48,6 +47,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/ARMTargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include <cstdio>
#ifdef CLANG_HAVE_RLIMITS
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 20de1b9b7bde96..20088d92bafa2f 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -15,8 +15,8 @@
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributeParser.h"
#include "llvm/Support/RISCVAttributes.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
using namespace llvm;
using namespace llvm::object;
diff --git a/llvm/include/llvm/Support/RISCVISAUtils.h b/llvm/include/llvm/Support/RISCVISAUtils.h
new file mode 100644
index 00000000000000..94aedb75faa256
--- /dev/null
+++ b/llvm/include/llvm/Support/RISCVISAUtils.h
@@ -0,0 +1,42 @@
+//===-- RISCVISAUtils.h - RISC-V ISA Utilities ------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Utilities shared by TableGen and RISCVISAInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_RISCVISAUTILS_H
+#define LLVM_SUPPORT_RISCVISAUTILS_H
+
+#include "llvm/ADT/StringRef.h"
+#include <string>
+
+namespace llvm {
+
+namespace RISCVISAUtils {
+constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
+
+/// Represents the major and version number components of a RISC-V extension.
+struct ExtensionVersion {
+ unsigned Major;
+ unsigned Minor;
+};
+
+bool compareExtension(const std::string &LHS, const std::string &RHS);
+
+/// Helper class for OrderedExtensionMap.
+struct ExtensionComparator {
+ bool operator()(const std::string &LHS, const std::string &RHS) const {
+ return compareExtension(LHS, RHS);
+ }
+};
+} // namespace RISCVISAUtils
+
+} // namespace llvm
+
+#endif
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
similarity index 86%
rename from llvm/include/llvm/Support/RISCVISAInfo.h
rename to llvm/include/llvm/TargetParser/RISCVISAInfo.h
index 46df93d7522602..83c4f1e620fc85 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -12,6 +12,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Error.h"
+#include "llvm/Support/RISCVISAUtils.h"
#include <map>
#include <string>
@@ -25,24 +26,10 @@ class RISCVISAInfo {
RISCVISAInfo(const RISCVISAInfo &) = delete;
RISCVISAInfo &operator=(const RISCVISAInfo &) = delete;
- /// Represents the major and version number components of a RISC-V extension.
- struct ExtensionVersion {
- unsigned Major;
- unsigned Minor;
- };
-
- static bool compareExtension(const std::string &LHS, const std::string &RHS);
-
- /// Helper class for OrderedExtensionMap.
- struct ExtensionComparator {
- bool operator()(const std::string &LHS, const std::string &RHS) const {
- return compareExtension(LHS, RHS);
- }
- };
-
/// OrderedExtensionMap is std::map, it's specialized to keep entries
/// in canonical order of extension.
- typedef std::map<std::string, ExtensionVersion, ExtensionComparator>
+ typedef std::map<std::string, RISCVISAUtils::ExtensionVersion,
+ RISCVISAUtils::ExtensionComparator>
OrderedExtensionMap;
RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts)
@@ -105,7 +92,7 @@ class RISCVISAInfo {
OrderedExtensionMap Exts;
- void addExtension(StringRef ExtName, ExtensionVersion Version);
+ void addExtension(StringRef ExtName, RISCVISAUtils::ExtensionVersion Version);
Error checkDependency();
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index efec612957de33..24d7a7a280fd9a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -24,7 +24,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/RISCVAttributeParser.h"
#include "llvm/Support/RISCVAttributes.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt
index e18beddf7bc5b7..03e888958a0711 100644
--- a/llvm/lib/Support/CMakeLists.txt
+++ b/llvm/lib/Support/CMakeLists.txt
@@ -219,7 +219,7 @@ add_llvm_component_library(LLVMSupport
Regex.cpp
RISCVAttributes.cpp
RISCVAttributeParser.cpp
- RISCVISAInfo.cpp
+ RISCVISAUtils.cpp
ScaledNumber.cpp
ScopedPrinter.cpp
SHA1.cpp
diff --git a/llvm/lib/Support/RISCVISAUtils.cpp b/llvm/lib/Support/RISCVISAUtils.cpp
new file mode 100644
index 00000000000000..ca7518f71907b5
--- /dev/null
+++ b/llvm/lib/Support/RISCVISAUtils.cpp
@@ -0,0 +1,88 @@
+//===-- RISCVISAUtils.cpp - RISC-V ISA Utilities --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Utilities shared by TableGen and RISCVISAInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/RISCVISAUtils.h"
+#include <cassert>
+
+using namespace llvm;
+
+// We rank extensions in the following order:
+// -Single letter extensions in canonical order.
+// -Unknown single letter extensions in alphabetical order.
+// -Multi-letter extensions starting with 'z' sorted by canonical order of
+// the second letter then sorted alphabetically.
+// -Multi-letter extensions starting with 's' in alphabetical order.
+// -(TODO) Multi-letter extensions starting with 'zxm' in alphabetical order.
+// -X extensions in alphabetical order.
+// These flags are used to indicate the category. The first 6 bits store the
+// single letter extension rank for single letter and multi-letter extensions
+// starting with 'z'.
+enum RankFlags {
+ RF_Z_EXTENSION = 1 << 6,
+ RF_S_EXTENSION = 1 << 7,
+ RF_X_EXTENSION = 1 << 8,
+};
+
+// Get the rank for single-letter extension, lower value meaning higher
+// priority.
+static unsigned singleLetterExtensionRank(char Ext) {
+ assert(Ext >= 'a' && Ext <= 'z');
+ switch (Ext) {
+ case 'i':
+ return 0;
+ case 'e':
+ return 1;
+ }
+
+ size_t Pos = RISCVISAUtils::AllStdExts.find(Ext);
+ if (Pos != StringRef::npos)
+ return Pos + 2; // Skip 'e' and 'i' from above.
+
+ // If we got an unknown extension letter, then give it an alphabetical
+ // order, but after all known standard extensions.
+ return 2 + RISCVISAUtils::AllStdExts.size() + (Ext - 'a');
+}
+
+// Get the rank for multi-letter extension, lower value meaning higher
+// priority/order in canonical order.
+static unsigned getExtensionRank(const std::string &ExtName) {
+ assert(ExtName.size() >= 1);
+ switch (ExtName[0]) {
+ case 's':
+ return RF_S_EXTENSION;
+ case 'z':
+ assert(ExtName.size() >= 2);
+ // `z` extension must be sorted by canonical order of second letter.
+ // e.g. zmx has higher rank than zax.
+ return RF_Z_EXTENSION | singleLetterExtensionRank(ExtName[1]);
+ case 'x':
+ return RF_X_EXTENSION;
+ default:
+ assert(ExtName.size() == 1);
+ return singleLetterExtensionRank(ExtName[0]);
+ }
+}
+
+// Compare function for extension.
+// Only compare the extension name, ignore version comparison.
+bool llvm::RISCVISAUtils::compareExtension(const std::string &LHS,
+ const std::string &RHS) {
+ unsigned LHSRank = getExtensionRank(LHS);
+ unsigned RHSRank = getExtensionRank(RHS);
+
+ // If the ranks differ, pick the lower rank.
+ if (LHSRank != RHSRank)
+ return LHSRank < RHSRank;
+
+ // If the rank is same, it must be sorted by lexicographic order.
+ return LHS < RHS;
+}
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d926ccdb59e19b..da5170ceeab01a 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -38,7 +38,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/RISCVAttributes.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include <limits>
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 67c9060b515772..4c59474df88358 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -16,7 +16,6 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/TargetParser.h"
#include "llvm/TargetParser/Triple.h"
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index aa641bc866aa5e..08f056f78979af 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -19,7 +19,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/SubtargetFeature.h"
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 4a4b1e13c2b9ec..0f92e9ed6a64d3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -16,7 +16,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/RISCVAttributes.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
using namespace llvm;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 779f179dff619f..6eceaddc747d15 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -37,8 +37,8 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
-#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
using namespace llvm;
diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt
index da1e352b037338..c100746c8c333f 100644
--- a/llvm/lib/TargetParser/CMakeLists.txt
+++ b/llvm/lib/TargetParser/CMakeLists.txt
@@ -20,6 +20,7 @@ add_llvm_component_library(LLVMTargetParser
CSKYTargetParser.cpp
Host.cpp
LoongArchTargetParser.cpp
+ RISCVISAInfo.cpp
RISCVTargetParser.cpp
SubtargetFeature.cpp
TargetParser.cpp
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
similarity index 93%
rename from llvm/lib/Support/RISCVISAInfo.cpp
rename to llvm/lib/TargetParser/RISCVISAInfo.cpp
index fa967403ea449c..c103449f8067b7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ------------*- C++ -*-===//
+//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
@@ -29,7 +29,7 @@ namespace {
struct RISCVSupportedExtension {
const char *Name;
/// Supported version.
- RISCVISAInfo::ExtensionVersion Version;
+ RISCVISAUtils::ExtensionVersion Version;
bool operator<(const RISCVSupportedExtension &RHS) const {
return StringRef(Name) < StringRef(RHS.Name);
@@ -43,8 +43,6 @@ struct RISCVProfile {
} // end anonymous namespace
-static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
-
static const char *RISCVGImplications[] = {
"i", "m", "a", "f", "d", "zicsr", "zifencei"
};
@@ -370,7 +368,7 @@ struct LessExtName {
};
} // namespace
-static std::optional<RISCVISAInfo::ExtensionVersion>
+static std::optional<RISCVISAUtils::ExtensionVersion>
findDefaultVersion(StringRef ExtName) {
// Find default version of an extension.
// TODO: We might set default version based on profile or ISA spec.
@@ -387,7 +385,7 @@ findDefaultVersion(StringRef ExtName) {
}
void RISCVISAInfo::addExtension(StringRef ExtName,
- RISCVISAInfo::ExtensionVersion Version) {
+ RISCVISAUtils::ExtensionVersion Version) {
Exts[ExtName.str()] = Version;
}
@@ -411,7 +409,7 @@ static StringRef getExtensionType(StringRef Ext) {
return StringRef();
}
-static std::optional<RISCVISAInfo::ExtensionVersion>
+static std::optional<RISCVISAUtils::ExtensionVersion>
isExperimentalExtension(StringRef Ext) {
auto I =
llvm::lower_bound(SupportedExperimentalExtensions, Ext, LessExtName());
@@ -468,78 +466,6 @@ bool RISCVISAInfo::hasExtension(StringRef Ext) const {
return Exts.count(Ext.str()) != 0;
}
-// We rank extensions in the following order:
-// -Single letter extensions in canonical order.
-// -Unknown single letter extensions in alphabetical order.
-// -Multi-letter extensions starting with 'z' sorted by canonical order of
-// the second letter then sorted alphabetically.
-// -Multi-letter extensions starting with 's' in alphabetical order.
-// -(TODO) Multi-letter extensions starting with 'zxm' in alphabetical order.
-// -X extensions in alphabetical order.
-// These flags are used to indicate the category. The first 6 bits store the
-// single letter extension rank for single letter and multi-letter extensions
-// starting with 'z'.
-enum RankFlags {
- RF_Z_EXTENSION = 1 << 6,
- RF_S_EXTENSION = 1 << 7,
- RF_X_EXTENSION = 1 << 8,
-};
-
-// Get the rank for single-letter extension, lower value meaning higher
-// priority.
-static unsigned singleLetterExtensionRank(char Ext) {
- assert(Ext >= 'a' && Ext <= 'z');
- switch (Ext) {
- case 'i':
- return 0;
- case 'e':
- return 1;
- }
-
- size_t Pos = AllStdExts.find(Ext);
- if (Pos != StringRef::npos)
- return Pos + 2; // Skip 'e' and 'i' from above.
-
- // If we got an unknown extension letter, then give it an alphabetical
- // order, but after all known standard extensions.
- return 2 + AllStdExts.size() + (Ext - 'a');
-}
-
-// Get the rank for multi-letter extension, lower value meaning higher
-// priority/order in canonical order.
-static unsigned getExtensionRank(const std::string &ExtName) {
- assert(ExtName.size() >= 1);
- switch (ExtName[0]) {
- case 's':
- return RF_S_EXTENSION;
- case 'z':
- assert(ExtName.size() >= 2);
- // `z` extension must be sorted by canonical order of second letter.
- // e.g. zmx has higher rank than zax.
- return RF_Z_EXTENSION | singleLetterExtensionRank(ExtName[1]);
- case 'x':
- return RF_X_EXTENSION;
- default:
- assert(ExtName.size() == 1);
- return singleLetterExtensionRank(ExtName[0]);
- }
-}
-
-// Compare function for extension.
-// Only compare the extension name, ignore version comparison.
-bool RISCVISAInfo::compareExtension(const std::string &LHS,
- const std::string &RHS) {
- unsigned LHSRank = getExtensionRank(LHS);
- unsigned RHSRank = getExtensionRank(RHS);
-
- // If the ranks differ, pick the lower rank.
- if (LHSRank != RHSRank)
- return LHSRank < RHSRank;
-
- // If the rank is same, it must be sorted by lexicographic order.
- return LHS < RHS;
-}
-
std::vector<std::string> RISCVISAInfo::toFeatures(bool AddAllExtensions,
bool IgnoreUnknown) const {
std::vector<std::string> Features;
@@ -808,7 +734,7 @@ static Error splitExtsByUnderscore(StringRef Exts,
static Error processMultiLetterExtension(
StringRef RawExt,
- MapVector<std::string, RISCVISAInfo::ExtensionVersion,
+ MapVector<std::string, RISCVISAUtils::ExtensionVersion,
std::map<std::string, unsigned>> &SeenExtMap,
bool IgnoreUnknown, bool EnableExperimentalExtension,
bool ExperimentalExtensionVersionCheck) {
@@ -854,7 +780,7 @@ static Error processMultiLetterExtension(
static Error processSingleLetterExtension(
StringRef &RawExt,
- MapVector<std::string, RISCVISAInfo::ExtensionVersion,
+ MapVector<std::string, RISCVISAUtils::ExtensionVersion,
std::map<std::string, unsigned>> &SeenExtMap,
bool IgnoreUnknown, bool EnableExperimentalExtension,
bool ExperimentalExtensionVersionCheck) {
@@ -930,7 +856,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
unsigned XLen = HasRV64 ? 64 : 32;
std::unique_ptr<RISCVISAInfo> ISAInfo(new RISCVISAInfo(XLen));
- MapVector<std::string, RISCVISAInfo::ExtensionVersion,
+ MapVector<std::string, RISCVISAUtils::ExtensionVersion,
std::map<std::string, unsigned>>
SeenExtMap;
@@ -1007,7 +933,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
for (auto &Ext : SplitExts) {
StringRef CurrExt = Ext;
while (!CurrExt.empty()) {
- if (AllStdExts.contains(CurrExt.front())) {
+ if (RISCVISAUtils::AllStdExts.contains(CurrExt.front())) {
if (auto E = processSingleLetterExtension(
CurrExt, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension,
ExperimentalExtensionVersionCheck))
@@ -1041,7 +967,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
// Check all Extensions are supported.
for (auto &SeenExtAndVers : SeenExtMap) {
const std::string &ExtName = SeenExtAndVers.first;
- RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second;
+ RISCVISAUtils::ExtensionVersion ExtVers = SeenExtAndVers.second;
if (!RISCVISAInfo::isSupportedExtension(ExtName))
return getStringErrorForInvalidExt(ExtName);
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 0d95e3a9b81962..9003f9beffa7e7 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,7 +14,7 @@
#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"
namespace llvm {
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index caf7bf0a317174..a1cc16ee61bdf9 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -15,8 +15,8 @@ using ::testing::ElementsAre;
using namespace llvm;
-bool operator==(const RISCVISAInfo::ExtensionVersion &A,
- const RISCVISAInfo::ExtensionVersion &B) {
+bool operator==(const RISCVISAUtils::ExtensionVersion &A,
+ const RISCVISAUtils::ExtensionVersion &B) {
return A.Major == B.Major && A.Minor == B.Minor;
}
@@ -51,7 +51,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) {
RISCVISAInfo &InfoRV32I = **MaybeRV32I;
EXPECT_EQ(InfoRV32I.getExtensions().size(), 1UL);
EXPECT_TRUE(InfoRV32I.getExtensions().at("i") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV32I.getXLen(), 32U);
auto MaybeRV32E = RISCVISAInfo::parseNormalizedArchString("rv32e2p0");
@@ -59,7 +59,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) {
RISCVISAInfo &InfoRV32E = **MaybeRV32E;
EXPECT_EQ(InfoRV32E.getExtensions().size(), 1UL);
EXPECT_TRUE(InfoRV32E.getExtensions().at("e") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV32E.getXLen(), 32U);
auto MaybeRV64I = RISCVISAInfo::parseNormalizedArchString("rv64i2p0");
@@ -67,7 +67,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) {
RISCVISAInfo &InfoRV64I = **MaybeRV64I;
EXPECT_EQ(InfoRV64I.getExtensions().size(), 1UL);
EXPECT_TRUE(InfoRV64I.getExtensions().at("i") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV64I.getXLen(), 64U);
auto MaybeRV64E = RISCVISAInfo::parseNormalizedArchString("rv64e2p0");
@@ -75,7 +75,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) {
RISCVISAInfo &InfoRV64E = **MaybeRV64E;
EXPECT_EQ(InfoRV64E.getExtensions().size(), 1UL);
EXPECT_TRUE(InfoRV64E.getExtensions().at("e") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV64E.getXLen(), 64U);
}
@@ -86,15 +86,15 @@ TEST(ParseNormalizedArchString, AcceptsArbitraryExtensionsAndVersions) {
RISCVISAInfo &Info = **MaybeISAInfo;
EXPECT_EQ(Info.getExtensions().size(), 5UL);
EXPECT_TRUE(Info.getExtensions().at("i") ==
- (RISCVISAInfo::ExtensionVersion{5, 1}));
+ (RISCVISAUtils::ExtensionVersion{5, 1}));
EXPECT_TRUE(Info.getExtensions().at("m") ==
- (RISCVISAInfo::ExtensionVersion{3, 2}));
+ (RISCVISAUtils::ExtensionVersion{3, 2}));
EXPECT_TRUE(Info.getExtensions().at("zmadeup") ==
- (RISCVISAInfo::ExtensionVersion{11, 12}));
+ (RISCVISAUtils::ExtensionVersion{11, 12}));
EXPECT_TRUE(Info.getExtensions().at("sfoo") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_TRUE(Info.getExtensions().at("xbar") ==
- (RISCVISAInfo::ExtensionVersion{3, 0}));
+ (RISCVISAUtils::ExtensionVersion{3, 0}));
}
TEST(ParseNormalizedArchString, UpdatesFLenMinVLenMaxELen) {
@@ -139,7 +139,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV32I = **MaybeRV32I;
RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions();
EXPECT_EQ(ExtsRV32I.size(), 1UL);
- EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
EXPECT_EQ(InfoRV32I.getXLen(), 32U);
EXPECT_EQ(InfoRV32I.getFLen(), 0U);
@@ -148,7 +148,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV32E = **MaybeRV32E;
RISCVISAInfo::OrderedExtensionMap ExtsRV32E = InfoRV32E.getExtensions();
EXPECT_EQ(ExtsRV32E.size(), 1UL);
- EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV32E.getXLen(), 32U);
EXPECT_EQ(InfoRV32E.getFLen(), 0U);
@@ -157,14 +157,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV32G = **MaybeRV32G;
RISCVISAInfo::OrderedExtensionMap ExtsRV32G = InfoRV32G.getExtensions();
EXPECT_EQ(ExtsRV32G.size(), 7UL);
- EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
- EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0}));
- EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1}));
- EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2}));
- EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2}));
- EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVISAUtils::ExtensionVersion{2, 2}));
+ EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVISAUtils::ExtensionVersion{2, 2}));
+ EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_TRUE(ExtsRV32G.at("zifencei") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV32G.getXLen(), 32U);
EXPECT_EQ(InfoRV32G.getFLen(), 64U);
@@ -173,7 +173,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV64I = **MaybeRV64I;
RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions();
EXPECT_EQ(ExtsRV64I.size(), 1UL);
- EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
EXPECT_EQ(InfoRV64I.getXLen(), 64U);
EXPECT_EQ(InfoRV64I.getFLen(), 0U);
@@ -182,7 +182,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV64E = **MaybeRV64E;
RISCVISAInfo::OrderedExtensionMap ExtsRV64E = InfoRV64E.getExtensions();
EXPECT_EQ(ExtsRV64E.size(), 1UL);
- EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV64E.getXLen(), 64U);
EXPECT_EQ(InfoRV64E.getFLen(), 0U);
@@ -191,14 +191,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV64G = **MaybeRV64G;
RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions();
EXPECT_EQ(ExtsRV64G.size(), 7UL);
- EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
- EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0}));
- EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1}));
- EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2}));
- EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2}));
- EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVISAUtils::ExtensionVersion{2, 2}));
+ EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVISAUtils::ExtensionVersion{2, 2}));
+ EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_TRUE(ExtsRV64G.at("zifencei") ==
- (RISCVISAInfo::ExtensionVersion{2, 0}));
+ (RISCVISAUtils::ExtensionVersion{2, 0}));
EXPECT_EQ(InfoRV64G.getXLen(), 64U);
EXPECT_EQ(InfoRV64G.getFLen(), 64U);
}
@@ -243,7 +243,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
RISCVISAInfo &Info = **MaybeISAInfo;
RISCVISAInfo::OrderedExtensionMap Exts = Info.getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
}
// Checks that supported extensions aren't incorrectly ignored when a
@@ -252,7 +252,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
RISCVISAInfo::parseArchString("rv32i_zbc1p0_xmadeup", true, false, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
- EXPECT_TRUE(Exts.at("zbc") == (RISCVISAInfo::ExtensionVersion{1, 0}));
+ EXPECT_TRUE(Exts.at("zbc") == (RISCVISAUtils::ExtensionVersion{1, 0}));
}
TEST(ParseArchString, AcceptsVersionInLongOrShortForm) {
@@ -260,13 +260,13 @@ TEST(ParseArchString, AcceptsVersionInLongOrShortForm) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
- EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
}
for (StringRef Input : {"rv32i_zfinx1", "rv32i_zfinx1p0"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
- EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAInfo::ExtensionVersion{1, 0}));
+ EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAUtils::ExtensionVersion{1, 0}));
}
}
@@ -295,14 +295,14 @@ TEST(ParseArchString,
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
}
for (StringRef Input : {"rv32e0p1", "rv32e99p99", "rv64e0p1", "rv64e99p99"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0}));
+ EXPECT_TRUE(Exts.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0}));
}
}
@@ -313,7 +313,7 @@ TEST(ParseArchString,
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1}));
}
}
@@ -481,7 +481,7 @@ TEST(ParseArchString,
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 2UL);
- EXPECT_TRUE(Exts.at("ztso") == (RISCVISAInfo::ExtensionVersion{9, 9}));
+ EXPECT_TRUE(Exts.at("ztso") == (RISCVISAUtils::ExtensionVersion{9, 9}));
}
TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) {
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 653e5c5fdb4219..26034e31ad8d19 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -24,8 +24,8 @@ using namespace llvm;
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
static void printMArch(raw_ostream &OS, const Record &Rec) {
- std::map<std::string, RISCVISAInfo::ExtensionVersion,
- RISCVISAInfo::ExtensionComparator>
+ std::map<std::string, RISCVISAUtils::ExtensionVersion,
+ RISCVISAUtils::ExtensionComparator>
Extensions;
unsigned XLen = 0;
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