[llvm] [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions (PR #89976)

Yingwei Zheng via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 24 23:22:21 PDT 2024

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https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/89976

Previous message: [llvm] [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions (PR #89976)
Next message: [llvm] promote PseduoCode from 32bit to 64bits after eliminating the `extsw` instruction in PPCMIPeepholes optimization (PR #85451)
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