[llvm] [RISCV] Add Sched classes for vector crypto instructions (PR #90068)

[Craig Topper via llvm-commits]

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@@ -57,8 +55,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
   def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
               (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
               opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
-         Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
-                ReadVMask]>;
+          SchedUnaryMC<"WriteVROR", "ReadVROR">;
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topperc wrote:

Established convention is a different Write based on the operand type. See `WriteVIALUV`, `WriteVIALUX`, and `WriteVIALUI`

https://github.com/llvm/llvm-project/pull/90068