[llvm] [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add (PR #89532)

[via llvm-commits]

================
@@ -410,6 +410,23 @@ define i32 @test11(i32 %x) {
   ret i32 %mul
 }
 
+define i32 @test11_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
+; CHECK-LABEL: test11_fast_shift:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add w8, w0, w0
----------------
vfdff wrote:

sorry for missing the shift amount, fixed.
Also add 2 negative cases whose shift amount are out of bound.

https://github.com/llvm/llvm-project/pull/89532