[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[Michael Maitland via llvm-commits]

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@@ -86,6 +86,16 @@ class ExegesisTarget {
                 ArrayRef<const char *> ValidationCounters,
                 const pid_t ProcessID = 0) const;
 
+  virtual bool checkOpcodeSupported(int Opcode,
+                                    const MCSubtargetInfo &SI) const {
+    return true;
+  }
+
+  // Find register by name, 0 if not found.
+  virtual unsigned findRegisterByName(const StringRef RegName) const {
+    return 0;
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michaelmaitland wrote:

Is it possible for a register to have the value 0? Why not `RISCV::NoRegister` for RISC-V? Thats what `RISCVAsmParser::matchRegisterNameHelper` returns when there is no match.

https://github.com/llvm/llvm-project/pull/89047