[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -2781,6 +2784,28 @@ struct RegPairInfo {
 
 } // end anonymous namespace
 
+static unsigned getPredicateAsCounterReg(unsigned Reg) {
+  switch (Reg) {
+  case AArch64::P8:
+    return AArch64::PN8;
+  case AArch64::P9:
+    return AArch64::PN9;
+  case AArch64::P10:
+    return AArch64::PN10;
+  case AArch64::P11:
+    return AArch64::PN11;
+  case AArch64::P12:
+    return AArch64::PN12;
+  case AArch64::P13:
+    return AArch64::PN13;
+  case AArch64::P14:
+    return AArch64::PN14;
+  case AArch64::P15:
+    return AArch64::PN15;
+  }
+  return 0;
+}
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momchil-velikov wrote:

Strictly speaking, there's no guarantee that these constants form a contiguous, increasing range from `P8` to `P15`, it's a side effect of tablegen internally using an ordered container for tablegen records, sorted alphabetically. That said, we already do such an arithmetic in a few places. :/ 

https://github.com/llvm/llvm-project/pull/77665