[llvm] [RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (PR #89602)

[Michael Maitland via llvm-commits]

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@@ -241,3 +241,89 @@ body:             |
     $x10 = COPY %6(s64)
     PseudoRET implicit $x10
 ...
+
+---
+name:            srl_and_needed
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
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michaelmaitland wrote:

I think you can drop this `registers` section since all registers have their register class specified below (i.e. `%0:gprb(s64)`)

https://github.com/llvm/llvm-project/pull/89602