[llvm] [RISCV] Codegen support for XCVbi extension (PR #89719)

[Craig Topper via llvm-commits]

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@@ -7608,6 +7608,15 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     TargetCC = DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType()));
   }
 
+  if (Subtarget.hasVendorXCVbi() &&
+      (CCVal == ISD::SETEQ || CCVal == ISD::SETNE) &&
+      isa<ConstantSDNode>(RHS)) {
+    int32_t RHSImm = cast<ConstantSDNode>(RHS)->getSExtValue();
+    if (isInt<5>(RHSImm)) {
+      SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
+      return DAG.getNode(RISCVISD::SELECTIMM_CC, DL, VT, Ops);
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topperc wrote:

Why do we need a new node? Can't we match simm5 operand to RISCVISD::SELECT_CC in tablegen like you did for BR_CC?

https://github.com/llvm/llvm-project/pull/89719