[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

sdesmalen-arm wrote:

> > I guess my point more widely was that when choosing a different calling convention (other than the one we currently implement), the choice of PN8 may not be right.
> 
> All right, how about this strategy:
> 
> * don't optimise for hypothetical calling conventions
> * in `determineCalleeSaves`, make sure we chose an already saved register, or, if there are none, choose `pn8` if the calling convention of the function is one where we know `pn8` is a callee saved register:
>   
>   * `AArch64_SVE_VectorCall`
>   * `AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0`
>   * `AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2`
>   
>   Not a correctness issue if we miss some.
> * everywhere else we use only `AFI->getPredicateRegForFillSpill() != 0` as the condition determining we can and should load/store in pairs

Sounds good. The function would otherwise be free to choose any register that is not used as an argument/return register and is not a reserved register, but I'm happy fixing it to pn8 with the checks you outlined above. Just in case, please add an assert that PN8 is not also a reserved register.

I'd also suggest wrapping the `AFI->getPredicateRegForFillSpill() != 0` in a function like `canUseMultiVectorLoadStore` (feel free to pick a different name) that combines it with `&& (Subtarget.hasSVE2p1() || Subtarget.hasSME2())`, to keep the logic in other places a bit simpler.

https://github.com/llvm/llvm-project/pull/77665