[llvm] 7840fa9 - [RISCV] Fix doPRE not checking for ignored AVLs

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2024-04-26T13:18:10+08:00
New Revision: 7840fa91a24ec7b9b771fd105ee1a9e1ba58837f

URL: https://github.com/llvm/llvm-project/commit/7840fa91a24ec7b9b771fd105ee1a9e1ba58837f
DIFF: https://github.com/llvm/llvm-project/commit/7840fa91a24ec7b9b771fd105ee1a9e1ba58837f.diff

LOG: [RISCV] Fix doPRE not checking for ignored AVLs

This fixes a crash introduced in 011a65353b8b4dc018541f86356f2dfa0f124f1a
that showed up when compiling with -mrvv-vector-bits=zvl. Beforehand, if a
basic block only contained vmv.s.x the AVL register in VSETVLIInfo would
have been NoRegister since it ignores VL.

In doPRE if AvailableInfo had a register AVL we checked that it dominated,
but coincidentally this failed for NoRegister. Now that the ignored AVL
case is separated out, check for it and bail.

As a side note, it turns out 011a65353b8b4dc018541f86356f2dfa0f124f1a is
less NFC than it seems as we can now do PRE on blocks where AvailableInfo's
AVL is VLMAX.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3feb7ec347543c..c40b9031543fe2 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1511,6 +1511,11 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
         return;
   }
 
+  // If the AVL isn't used in its predecessors then bail, since we have no AVL
+  // to insert a vsetvli with.
+  if (AvailableInfo.hasAVLIgnored())
+    return;
+
   // Model the effect of changing the input state of the block MBB to
   // AvailableInfo.  We're looking for two issues here; one legality,
   // one profitability.

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
index 596ea1c39fcea8..16c4a1a0a89ec2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
@@ -130,6 +130,10 @@
     ret void
   }
 
+  define void @pre_undemanded_vl() {
+    ret void
+  }
+
   declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
 
   declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
@@ -1041,3 +1045,12 @@ body:             |
     PseudoRET
 
 ...
+---
+name: pre_undemanded_vl
+body: |
+  bb.0:
+    PseudoBR %bb.1
+  bb.1:
+    %x:gpr = PseudoVMV_X_S undef $noreg, 6
+    PseudoBR %bb.1
+...