[llvm] [RISCV] Remove -riscv-split-regalloc flag (PR #89715)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/89715

Split vector and scalar regalloc has been enabled by default for 5 months now since d0a39e617ba301a76d28e2d82e1f657999c9dcfb, and shipped with 18.1.0. I haven't heard of any issues with it so far, so this proposes to remove the flag to reduce the number of configurations we have to support.


>From e091b9ba89fadf025b7d4b843706b6c119c6fc2c Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 23 Apr 2024 16:05:48 +0800
Subject: [PATCH] [RISCV] Remove -riscv-split-regalloc flag

Split vector and scalar regalloc has been enabled by default for 5 months now since d0a39e617ba301a76d28e2d82e1f657999c9dcfb, and shipped with 18.1.0. I haven't heard of any issues with it so far, so this proposes to remove the flag to reduce the number of configurations we have to support.
---
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index ae1a6f179a49e3..34ddd635231087 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -91,11 +91,6 @@ static cl::opt<bool>
                            cl::desc("Enable the loop data prefetch pass"),
                            cl::init(true));
 
-static cl::opt<bool>
-    EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
-                        cl::desc("Enable Split RegisterAlloc for RVV"),
-                        cl::init(true));
-
 static cl::opt<bool> EnableMISchedLoadClustering(
     "riscv-misched-load-clustering", cl::Hidden,
     cl::desc("Enable load clustering in the machine scheduler"),
@@ -392,16 +387,13 @@ FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
 }
 
 bool RISCVPassConfig::addRegAssignAndRewriteFast() {
-  if (EnableSplitRegAlloc)
-    addPass(createRVVRegAllocPass(false));
+  addPass(createRVVRegAllocPass(false));
   return TargetPassConfig::addRegAssignAndRewriteFast();
 }
 
 bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
-  if (EnableSplitRegAlloc) {
-    addPass(createRVVRegAllocPass(true));
-    addPass(createVirtRegRewriter(false));
-  }
+  addPass(createRVVRegAllocPass(true));
+  addPass(createVirtRegRewriter(false));
   return TargetPassConfig::addRegAssignAndRewriteOptimized();
 }