[llvm] [WIP][DAG] Introduce generic shl_add node [NFC] (PR #88791)

[Philip Reames via llvm-commits]

================
@@ -46905,12 +46897,18 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ResLo, ResHi);
 }
 
+static SDValue createMulImm(uint64_t MulAmt, SDValue N, SelectionDAG &DAG,
+                            EVT VT, const SDLoc &DL) {
+  assert(MulAmt == 3 || MulAmt == 5 || MulAmt == 9);
+  SDValue ShAmt = DAG.getConstant(Log2_64(MulAmt - 1), DL, MVT::i8);
+  return DAG.getNode(ISD::SHL_ADD, DL, VT, N, ShAmt, N);
----------------
preames wrote:

I investigated these differences further.  Net result is one fairly obvious missed optimization, one somewhat complicated but reasonable issue with COPY elimination, and one fundamental issue.  I'm going to focus on only the last.

We end up with a situation where an inserted freeze gets hoisted through a chain of computation.  This is all correct and fine, but as a side effect of that hoisting, we strip nsw off an add.  The net result is that we can't prove a narrow addressing sequence is equivalent to the wider form, and thus fail to be able to fold a constant base offset into the addressing mode.  

I'm a bit stuck on what to do about this case, and need to give this more thought.  


https://github.com/llvm/llvm-project/pull/88791