[llvm] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (PR #90208)
Zhijin Zeng via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 26 10:03:46 PDT 2024
https://github.com/zengdage updated https://github.com/llvm/llvm-project/pull/90208
>From 6cac8a7f124864a07593bc524f32e76135b02fa1 Mon Sep 17 00:00:00 2001
From: Zhijin Zeng <zhijin.zeng at spacemit.com>
Date: Fri, 26 Apr 2024 22:46:02 +0800
Subject: [PATCH 1/2] [RISC-V][Isel] Add new test case for czero.eqz
Signed-off-by: Zhijin Zeng <zhijin.zeng at spacemit.com>
---
llvm/test/CodeGen/RISCV/select.ll | 116 ++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index e07e52091e9e71..d056a6ba9938c5 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -1858,3 +1858,119 @@ define i32 @select_cst6(i1 zeroext %cond) {
%ret = select i1 %cond, i32 2049, i32 2047
ret i32 %ret
}
+
+ at select_redundant_czero_eqz_data = global i32 0, align 4
+
+define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
+; RV32IM-LABEL: select_redundant_czero_eqz1:
+; RV32IM: # %bb.0: # %entry
+; RV32IM-NEXT: bnez a0, .LBB49_2
+; RV32IM-NEXT: # %bb.1:
+; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
+; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV32IM-NEXT: .LBB49_2: # %entry
+; RV32IM-NEXT: sw a0, 0(a1)
+; RV32IM-NEXT: ret
+;
+; RV64IM-LABEL: select_redundant_czero_eqz1:
+; RV64IM: # %bb.0: # %entry
+; RV64IM-NEXT: bnez a0, .LBB49_2
+; RV64IM-NEXT: # %bb.1:
+; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
+; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV64IM-NEXT: .LBB49_2: # %entry
+; RV64IM-NEXT: sd a0, 0(a1)
+; RV64IM-NEXT: ret
+;
+; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz1:
+; RV64IMXVTCONDOPS: # %bb.0: # %entry
+; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
+; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
+; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0
+; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
+; RV64IMXVTCONDOPS-NEXT: ret
+;
+; RV32IMZICOND-LABEL: select_redundant_czero_eqz1:
+; RV32IMZICOND: # %bb.0: # %entry
+; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
+; RV32IMZICOND-NEXT: or a0, a2, a0
+; RV32IMZICOND-NEXT: sw a0, 0(a1)
+; RV32IMZICOND-NEXT: ret
+;
+; RV64IMZICOND-LABEL: select_redundant_czero_eqz1:
+; RV64IMZICOND: # %bb.0: # %entry
+; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
+; RV64IMZICOND-NEXT: or a0, a2, a0
+; RV64IMZICOND-NEXT: sd a0, 0(a1)
+; RV64IMZICOND-NEXT: ret
+entry:
+ %3 = icmp eq ptr %0, null
+ %4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0
+ store ptr %4, ptr %1, align 8
+ ret void
+}
+
+define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
+; RV32IM-LABEL: select_redundant_czero_eqz2:
+; RV32IM: # %bb.0: # %entry
+; RV32IM-NEXT: bnez a0, .LBB50_2
+; RV32IM-NEXT: # %bb.1: # %entry
+; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
+; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV32IM-NEXT: .LBB50_2: # %entry
+; RV32IM-NEXT: sw a0, 0(a1)
+; RV32IM-NEXT: ret
+;
+; RV64IM-LABEL: select_redundant_czero_eqz2:
+; RV64IM: # %bb.0: # %entry
+; RV64IM-NEXT: bnez a0, .LBB50_2
+; RV64IM-NEXT: # %bb.1: # %entry
+; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
+; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV64IM-NEXT: .LBB50_2: # %entry
+; RV64IM-NEXT: sd a0, 0(a1)
+; RV64IM-NEXT: ret
+;
+; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz2:
+; RV64IMXVTCONDOPS: # %bb.0: # %entry
+; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
+; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
+; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2
+; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
+; RV64IMXVTCONDOPS-NEXT: ret
+;
+; RV32IMZICOND-LABEL: select_redundant_czero_eqz2:
+; RV32IMZICOND: # %bb.0: # %entry
+; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
+; RV32IMZICOND-NEXT: or a0, a0, a2
+; RV32IMZICOND-NEXT: sw a0, 0(a1)
+; RV32IMZICOND-NEXT: ret
+;
+; RV64IMZICOND-LABEL: select_redundant_czero_eqz2:
+; RV64IMZICOND: # %bb.0: # %entry
+; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
+; RV64IMZICOND-NEXT: or a0, a0, a2
+; RV64IMZICOND-NEXT: sd a0, 0(a1)
+; RV64IMZICOND-NEXT: ret
+entry:
+ %3 = icmp ne ptr %0, null
+ %4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data
+ store ptr %4, ptr %1, align 8
+ ret void
+}
>From 05b2bc641505da1eb018c9fe1d5489e26afe3876 Mon Sep 17 00:00:00 2001
From: Zhijin Zeng <zhijin.zeng at spacemit.com>
Date: Fri, 26 Apr 2024 20:50:13 +0800
Subject: [PATCH 2/2] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz
a0, a0, a0'
Signed-off-by: Zhijin Zeng <zhijin.zeng at spacemit.com>
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 19 +++++++++++++++++++
llvm/test/CodeGen/RISCV/select.ll | 12 +++---------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 769c465d56f984..71a0692a2bba7d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7503,6 +7503,25 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal);
}
+ if (CondV.getOpcode() == ISD::SETCC) {
+ SDValue LHS = CondV.getOperand(0);
+ SDValue RHS = CondV.getOperand(1);
+ ISD::CondCode CCVal = cast<CondCodeSDNode>(CondV.getOperand(2))->get();
+ if (isNullConstant(RHS)) {
+ // c = setcc f, 0, seteq
+ // (select c, t, f) -> (or f, (czero_nez t, f))
+ if (CCVal == ISD::SETEQ && LHS == FalseV)
+ return DAG.getNode(
+ ISD::OR, DL, VT, FalseV,
+ DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, TrueV, LHS));
+ // c = setcc t, 0, setne
+ // (select c, t, f) -> (or t, (czero_nez f, t))
+ if (CCVal == ISD::SETNE && LHS == TrueV)
+ return DAG.getNode(
+ ISD::OR, DL, VT, TrueV,
+ DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, LHS));
+ }
+ }
// (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
// Unless we have the short forward branch optimization.
if (!Subtarget.hasConditionalMoveFusion())
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index d056a6ba9938c5..01938da3e74258 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -1887,8 +1887,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
-; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
-; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0
+; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2
; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
; RV64IMXVTCONDOPS-NEXT: ret
;
@@ -1897,8 +1896,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
-; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
-; RV32IMZICOND-NEXT: or a0, a2, a0
+; RV32IMZICOND-NEXT: or a0, a0, a2
; RV32IMZICOND-NEXT: sw a0, 0(a1)
; RV32IMZICOND-NEXT: ret
;
@@ -1907,8 +1905,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
-; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
-; RV64IMZICOND-NEXT: or a0, a2, a0
+; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
entry:
@@ -1944,7 +1941,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
-; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2
; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
; RV64IMXVTCONDOPS-NEXT: ret
@@ -1954,7 +1950,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
-; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
; RV32IMZICOND-NEXT: or a0, a0, a2
; RV32IMZICOND-NEXT: sw a0, 0(a1)
; RV32IMZICOND-NEXT: ret
@@ -1964,7 +1959,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
-; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
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