[llvm] [RISCV] Codegen support for XCVbi extension (PR #89719)

[Craig Topper via llvm-commits]

================
@@ -18035,6 +18053,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
            "ReadCounterWide is only to be used on riscv32");
     return emitReadCounterWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
+  case RISCV::Select_IMM_Using_CC_GPR:
----------------
topperc wrote:

This is misnamed. It should be `Select_GPR_Using_CC_Imm`. The first type is the of the register the instruction produces.

https://github.com/llvm/llvm-project/pull/89719