[llvm] [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add (PR #89532)

[via llvm-commits]

vfdff wrote:

Thank you for your reminder.
Yes, the transformation is not need for recent cores. But for some old cores, such as tsv110, it will be benifit from this conversion.
So it seems reasonable when this conversion associated with `FeatureALULSLFast`.
 -  mul: `the latency is 3~4, the throughout is 1` depend the register width
 -  adds: `the latency is 1, the throughout is 2` depend the register width
 > https://github.com/llvm/llvm-project/blob/b8e97f0768f2b537c45930f56f4027a4c0a07f24/llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s#L1830C10-L1830C71

https://github.com/llvm/llvm-project/pull/89532