[llvm] [AMDGPU] Fix mode register pass for constrained FP operations (PR #90085)

[Abhinav Garg via llvm-commits]

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@@ -9,8 +9,7 @@ define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 {
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
-; GCN-NEXT:    s_nop 1
-; GCN-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
+; GCN-NOT:     s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
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abhigargrepo wrote:

Okay

https://github.com/llvm/llvm-project/pull/90085