[llvm] [RISCV] Generate RISCVISAInfo table from RISCVFeatures.td. (PR #89955)

[Pengcheng Wang via llvm-commits]

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@@ -101,5 +197,10 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
   OS << "\n#undef TUNE_PROC\n";
 }
 
+static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+  emitRISCVExtensions(RK, OS);
+  emitRISCVProcs(RK, OS);
+}
+
 static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
                                 "Generate the list of CPU for RISCV");
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wangpc-pp wrote:

This help info is not correct now, and maybe there are more places (like comments in line 9-10) to reword.

https://github.com/llvm/llvm-project/pull/89955