[llvm] [AMDGPU] Fix mode register pass for constrained FP operations (PR #90085)

[Matt Arsenault via llvm-commits]

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@@ -430,6 +430,9 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
 }
 
 bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
+  const Function &F = MF.getFunction();
+  if (F.hasFnAttribute(llvm::Attribute::StrictFP))
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arsenm wrote:

This comment doesn't really explain why though. Should say something about how strictfp functions have user managed FP modes

https://github.com/llvm/llvm-project/pull/90085