[llvm] [RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (PR #89602)

[Michael Maitland via llvm-commits]

================
@@ -241,3 +241,89 @@ body:             |
     $x10 = COPY %6(s64)
     PseudoRET implicit $x10
 ...
+
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michaelmaitland wrote:

Could we have a case where
```
1. the lowest log2(XLEN) bits of the and mask are all set
2. the bits of the register being masked are already unset (zero set)
```
on rv32? If so, should we add rv32 tests for this?

https://github.com/llvm/llvm-project/pull/89602