[llvm] [Mips] Delete ISA conditional judgment in unsigned atomic max/min extend (PR #89881)

[via llvm-commits]

https://github.com/yingopq created https://github.com/llvm/llvm-project/pull/89881

About unsigned max/min, ANDi is available for all ISA revisions in extend before slt insn.

>From 0897900272b08878882dca1acd0c1b19d1c45d7a Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Wed, 24 Apr 2024 02:28:44 -0400
Subject: [PATCH] [Mips] Delete ISA conditional judgment in unsigned atomic
 max/min extend

About unsigned max/min, ANDi is available for all ISA revisions in
extend before slt insn.
---
 llvm/lib/Target/Mips/MipsExpandPseudo.cpp |  6 +++---
 llvm/test/CodeGen/Mips/atomic-min-max.ll  | 12 ++++--------
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index d33852a04baf0d..199474fbd82d75 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -479,13 +479,13 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
     BuildMI(loopMBB, DL, TII->get(Mips::SRAV), StoreVal)
         .addReg(OldVal)
         .addReg(ShiftAmnt);
-    if (STI->hasMips32r2() && !IsUnsigned) {
-      BuildMI(loopMBB, DL, TII->get(SEOp), StoreVal).addReg(StoreVal);
-    } else if (STI->hasMips32r2() && IsUnsigned) {
+    if (IsUnsigned) {
       const unsigned OpMask = SEOp == Mips::SEH ? 0xffff : 0xff;
       BuildMI(loopMBB, DL, TII->get(Mips::ANDi), StoreVal)
           .addReg(StoreVal)
           .addImm(OpMask);
+    } else if (STI->hasMips32r2()) {
+      BuildMI(loopMBB, DL, TII->get(SEOp), StoreVal).addReg(StoreVal);
     } else {
       const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
       const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA;
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index 2f07d70808c16a..3d3225509d1ae1 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -2156,8 +2156,7 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) {
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS32-NEXT:    ll $2, 0($6)
 ; MIPS32-NEXT:    srav $4, $2, $10
-; MIPS32-NEXT:    sll $4, $4, 16
-; MIPS32-NEXT:    srl $4, $4, 16
+; MIPS32-NEXT:    andi $4, $4, 65535
 ; MIPS32-NEXT:    or $1, $zero, $4
 ; MIPS32-NEXT:    sllv $4, $4, $10
 ; MIPS32-NEXT:    sltu $5, $4, $7
@@ -2695,8 +2694,7 @@ define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) {
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS32-NEXT:    ll $2, 0($6)
 ; MIPS32-NEXT:    srav $4, $2, $10
-; MIPS32-NEXT:    sll $4, $4, 16
-; MIPS32-NEXT:    srl $4, $4, 16
+; MIPS32-NEXT:    andi $4, $4, 65535
 ; MIPS32-NEXT:    or $1, $zero, $4
 ; MIPS32-NEXT:    sllv $4, $4, $10
 ; MIPS32-NEXT:    sltu $5, $4, $7
@@ -4313,8 +4311,7 @@ define i8 @test_umax_8(ptr nocapture %ptr, i8 signext %val) {
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS32-NEXT:    ll $2, 0($6)
 ; MIPS32-NEXT:    srav $4, $2, $10
-; MIPS32-NEXT:    sll $4, $4, 24
-; MIPS32-NEXT:    srl $4, $4, 24
+; MIPS32-NEXT:    andi $4, $4, 255
 ; MIPS32-NEXT:    or $1, $zero, $4
 ; MIPS32-NEXT:    sllv $4, $4, $10
 ; MIPS32-NEXT:    sltu $5, $4, $7
@@ -4852,8 +4849,7 @@ define i8 @test_umin_8(ptr nocapture %ptr, i8 signext %val) {
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS32-NEXT:    ll $2, 0($6)
 ; MIPS32-NEXT:    srav $4, $2, $10
-; MIPS32-NEXT:    sll $4, $4, 24
-; MIPS32-NEXT:    srl $4, $4, 24
+; MIPS32-NEXT:    andi $4, $4, 255
 ; MIPS32-NEXT:    or $1, $zero, $4
 ; MIPS32-NEXT:    sllv $4, $4, $10
 ; MIPS32-NEXT:    sltu $5, $4, $7