[llvm] 31af5e9 - AtomicExpand: Emit or with constant on RHS
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 06:00:41 PDT 2024
Author: Matt Arsenault
Date: 2024-04-23T15:00:31+02:00
New Revision: 31af5e9001508dd2e58d2232e900adba01896736
URL: https://github.com/llvm/llvm-project/commit/31af5e9001508dd2e58d2232e900adba01896736
DIFF: https://github.com/llvm/llvm-project/commit/31af5e9001508dd2e58d2232e900adba01896736.diff
LOG: AtomicExpand: Emit or with constant on RHS
This will save later code from commuting it.
Added:
Modified:
llvm/lib/CodeGen/AtomicExpandPass.cpp
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/atomic-signext.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp
index 0aa89ea94335dc..e5496c0e31c1c0 100644
--- a/llvm/lib/CodeGen/AtomicExpandPass.cpp
+++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp
@@ -943,7 +943,7 @@ AtomicRMWInst *AtomicExpandImpl::widenPartwordAtomicRMW(AtomicRMWInst *AI) {
if (Op == AtomicRMWInst::And)
NewOperand =
- Builder.CreateOr(PMV.Inv_Mask, ValOperand_Shifted, "AndOperand");
+ Builder.CreateOr(ValOperand_Shifted, PMV.Inv_Mask, "AndOperand");
else
NewOperand = ValOperand_Shifted;
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index fe530017406133..4871622ec23637 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2950,7 +2950,7 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
+; RV32IA-NEXT: or a1, a1, a3
; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret
@@ -2974,7 +2974,7 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NOZACAS-NEXT: not a3, a3
; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-NOZACAS-NEXT: ret
@@ -2988,7 +2988,7 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-ZACAS-NEXT: not a3, a3
; RV64IA-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-ZACAS-NEXT: or a1, a1, a3
; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-ZACAS-NEXT: ret
@@ -3026,7 +3026,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32IA-WMO-NEXT: not a3, a3
; RV32IA-WMO-NEXT: andi a1, a1, 255
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: or a1, a1, a3
; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -3040,7 +3040,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32IA-TSO-NEXT: not a3, a3
; RV32IA-TSO-NEXT: andi a1, a1, 255
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: or a1, a1, a3
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -3064,7 +3064,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -3078,7 +3078,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -3092,7 +3092,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a3, a3
; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -3106,7 +3106,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a3, a3
; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -3144,7 +3144,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV32IA-WMO-NEXT: not a3, a3
; RV32IA-WMO-NEXT: andi a1, a1, 255
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: or a1, a1, a3
; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -3158,7 +3158,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV32IA-TSO-NEXT: not a3, a3
; RV32IA-TSO-NEXT: andi a1, a1, 255
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: or a1, a1, a3
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -3182,7 +3182,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -3196,7 +3196,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -3210,7 +3210,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a3, a3
; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -3224,7 +3224,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a3, a3
; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -3262,7 +3262,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32IA-WMO-NEXT: not a3, a3
; RV32IA-WMO-NEXT: andi a1, a1, 255
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: or a1, a1, a3
; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -3276,7 +3276,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32IA-TSO-NEXT: not a3, a3
; RV32IA-TSO-NEXT: andi a1, a1, 255
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: or a1, a1, a3
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -3300,7 +3300,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -3314,7 +3314,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -3328,7 +3328,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a3, a3
; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -3342,7 +3342,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a3, a3
; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -3380,7 +3380,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32IA-WMO-NEXT: not a3, a3
; RV32IA-WMO-NEXT: andi a1, a1, 255
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: or a1, a1, a3
; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -3394,7 +3394,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32IA-TSO-NEXT: not a3, a3
; RV32IA-TSO-NEXT: andi a1, a1, 255
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: or a1, a1, a3
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -3418,7 +3418,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -3432,7 +3432,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -3446,7 +3446,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a3, a3
; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -3460,7 +3460,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a3, a3
; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -12863,7 +12863,7 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
+; RV32IA-NEXT: or a1, a1, a4
; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret
@@ -12888,7 +12888,7 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NOZACAS-NEXT: not a4, a4
; RV64IA-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-NOZACAS-NEXT: ret
@@ -12903,7 +12903,7 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-ZACAS-NEXT: not a4, a4
; RV64IA-ZACAS-NEXT: and a1, a1, a3
; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-ZACAS-NEXT: or a1, a1, a4
; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-ZACAS-NEXT: ret
@@ -12942,7 +12942,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32IA-WMO-NEXT: not a4, a4
; RV32IA-WMO-NEXT: and a1, a1, a3
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: or a1, a1, a4
; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -12957,7 +12957,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32IA-TSO-NEXT: not a4, a4
; RV32IA-TSO-NEXT: and a1, a1, a3
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: or a1, a1, a4
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -12982,7 +12982,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -12997,7 +12997,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -13012,7 +13012,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a4, a4
; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -13027,7 +13027,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a4, a4
; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -13066,7 +13066,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV32IA-WMO-NEXT: not a4, a4
; RV32IA-WMO-NEXT: and a1, a1, a3
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: or a1, a1, a4
; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -13081,7 +13081,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV32IA-TSO-NEXT: not a4, a4
; RV32IA-TSO-NEXT: and a1, a1, a3
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: or a1, a1, a4
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -13106,7 +13106,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -13121,7 +13121,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -13136,7 +13136,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a4, a4
; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -13151,7 +13151,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a4, a4
; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -13190,7 +13190,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32IA-WMO-NEXT: not a4, a4
; RV32IA-WMO-NEXT: and a1, a1, a3
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: or a1, a1, a4
; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -13205,7 +13205,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32IA-TSO-NEXT: not a4, a4
; RV32IA-TSO-NEXT: and a1, a1, a3
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: or a1, a1, a4
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -13230,7 +13230,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -13245,7 +13245,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -13260,7 +13260,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a4, a4
; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -13275,7 +13275,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a4, a4
; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
@@ -13314,7 +13314,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32IA-WMO-NEXT: not a4, a4
; RV32IA-WMO-NEXT: and a1, a1, a3
; RV32IA-WMO-NEXT: sll a1, a1, a0
-; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: or a1, a1, a4
; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-WMO-NEXT: srl a0, a1, a0
; RV32IA-WMO-NEXT: ret
@@ -13329,7 +13329,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32IA-TSO-NEXT: not a4, a4
; RV32IA-TSO-NEXT: and a1, a1, a3
; RV32IA-TSO-NEXT: sll a1, a1, a0
-; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: or a1, a1, a4
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
; RV32IA-TSO-NEXT: ret
@@ -13354,7 +13354,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-NOZACAS-NEXT: ret
@@ -13369,7 +13369,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-NOZACAS-NEXT: ret
@@ -13384,7 +13384,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64IA-WMO-ZACAS-NEXT: not a4, a4
; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-WMO-ZACAS-NEXT: ret
@@ -13399,7 +13399,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: not a4, a4
; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: or a1, a1, a4
; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
; RV64IA-TSO-ZACAS-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index bdf3b28d2d523b..f7268f62881276 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -362,7 +362,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
+; RV32IA-NEXT: or a1, a1, a3
; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: slli a0, a0, 24
@@ -390,7 +390,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
+; RV64IA-NEXT: or a1, a1, a3
; RV64IA-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: slli a0, a0, 56
@@ -1403,7 +1403,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
+; RV32IA-NEXT: or a1, a1, a4
; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: slli a0, a0, 16
@@ -1432,7 +1432,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
+; RV64IA-NEXT: or a1, a1, a4
; RV64IA-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: slli a0, a0, 48
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
index 08d990fb58039e..78468b933ff5b2 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll
@@ -152,7 +152,7 @@ define i16 @test_atomicrmw_and_i16_global_system(ptr addrspace(1) %ptr, i16 %val
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
index 94f1b733877ed7..3806159ab7303c 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
@@ -153,7 +153,7 @@ define i16 @test_atomicrmw_and_i16_global_agent(ptr addrspace(1) %ptr, i16 %valu
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
index 80cf19ed8c636a..088371f461ec11 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll
@@ -161,7 +161,7 @@ define i8 @test_atomicrmw_and_i8_global_system(ptr addrspace(1) %ptr, i8 %value)
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
index 711580158e7251..97651c8d23a1e0 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
@@ -264,7 +264,7 @@ define i8 @test_atomicrmw_and_i8_global_agent(ptr addrspace(1) %ptr, i8 %value)
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; GCN-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; GCN-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; GCN-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; GCN-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; GCN-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
; GCN-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; GCN-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
@@ -279,7 +279,7 @@ define i8 @test_atomicrmw_and_i8_global_agent(ptr addrspace(1) %ptr, i8 %value)
; R600-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; R600-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; R600-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[TMP2]]
-; R600-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; R600-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; R600-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
; R600-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[TMP2]]
; R600-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
index e8be1bc1874836..3a306a4d98613b 100644
--- a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
+++ b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
@@ -220,7 +220,7 @@ define i16 @test_and_i16(ptr %arg, i16 %val) {
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
+; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
@@ -262,18 +262,18 @@ define i16 @test_min_i16(ptr %arg, i16 %val) {
; CHECK-NEXT: [[TMP4:%.*]] = icmp sle i16 [[EXTRACTED]], [[VAL:%.*]]
; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP4]], i16 [[EXTRACTED]], i16 [[VAL]]
; CHECK-NEXT: [[EXTENDED:%.*]] = zext i16 [[NEW]] to i32
-; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
+; CHECK-NEXT: [[SHIFTED1:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
-; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
+; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED1]]
; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK: atomicrmw.end:
-; CHECK-NEXT: [[SHIFTED3:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
-; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
+; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
+; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: ret i16 [[EXTRACTED4]]
+; CHECK-NEXT: ret i16 [[EXTRACTED3]]
;
entry:
%ret = atomicrmw min ptr %arg, i16 %val seq_cst
@@ -301,17 +301,17 @@ define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) {
; CHECK-NEXT: [[NEW:%.*]] = fadd half [[TMP5]], [[VALUE:%.*]]
; CHECK-NEXT: [[TMP6:%.*]] = bitcast half [[NEW]] to i16
; CHECK-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP6]] to i32
-; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
+; CHECK-NEXT: [[SHIFTED1:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
-; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
+; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED1]]
; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK: atomicrmw.end:
-; CHECK-NEXT: [[SHIFTED3:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
-; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
-; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
+; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
+; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16
+; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED3]] to half
; CHECK-NEXT: fence seq_cst
; CHECK-NEXT: ret half [[TMP8]]
;
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