[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

================
@@ -3333,14 +3379,28 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
         ExtraCSSpill = PairedReg;
     }
 
-    // If ZPR has pair registers and predicate register is not reserved, save it
-    // because it will be clobbered in spillCalleeSavedRegisters and
-    // restoreCalleeSavedRegisters
-    if (Subtarget.hasSVE2p1() || Subtarget.hasSME2())
-      if (AArch64::ZPRRegClass.contains(Reg, CSRegs[i ^ 1]) &&
-          SavedRegs.test(CSRegs[i ^ 1]) &&
-          !RegInfo->isReservedReg(MF, AArch64::P8))
-        SavedRegs.set(AArch64::P8);
+    // Save PReg in FunctionInfo to build PTRUE instruction later. The PTRUE is
+    // being used in the function to save and restore the pair of ZReg
+    AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+    if (Subtarget.hasSVE2p1() || Subtarget.hasSME2()) {
+      if (AArch64::PPRRegClass.contains(Reg) &&
+          (Reg > AArch64::P8 || Reg < AArch64::P15) && SavedRegs.test(Reg) &&
----------------
momchil-velikov wrote:

Looks like that should be `Reg >= AArch64::P8 && Reg <= AArch64::P15`

https://github.com/llvm/llvm-project/pull/77665