[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 28 03:25:51 PDT 2024
=?utf-8?b?6YOd5bq36L6+?= <hebo at bosc.ac.cn>
Message-ID: <llvm.org/llvm/llvm-project/pull/90392 at github.com>
In-Reply-To:
https://github.com/Bhe6669 created https://github.com/llvm/llvm-project/pull/90392
The "XiangShan" is a high-performance open-source RISC-V processor project, and The "KunMingHu" architecture is its third generation. Official documentation can be found at:[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/).
Currently, the KunMingHu core supports"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei". The scheduling model encompasses the basic configurations and instruction latencies of the KunMingHu core. Other components will be submitted in subsequent patches.
Co-authored-by:
Chen Jian<chenjian at bosc.ac.cn>
Lv Fang<lvfang at bosc.ac.cn>
>From 96b67d0d55b9e2daac17179cd239b2e54ab5ab0b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=83=9D=E5=BA=B7=E8=BE=BE?= <hebo at bosc.ac.cn>
Date: Sun, 28 Apr 2024 18:15:05 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-KunMingHu
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This pull request adds definitions for the XiangShan-KunMingHu processor. "XiangShan" is a high-performance open-source RISC-V processor project, and "KunMingHu" architecture is its third generation. Official documentation can be found at: [documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/).
Currently, the KunMingHu core supports"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei". The scheduler model and other components will be submitted in subsequent patches.
Co-authored-by:
Chen Jian<chenjian at bosc.ac.cn>
Lv Fang<lvfang at bosc.ac.cn>
Co-Authored-By: Khao7342 <167075369+Khao7342 at users.noreply.github.com>
Co-Authored-By: huxuan0307 <39661208+huxuan0307 at users.noreply.github.com>
Co-Authored-By: Ziyue-Zhang <46214232+Ziyue-Zhang at users.noreply.github.com>
Co-Authored-By: Lin Wang <38717023+MrLinWang at users.noreply.github.com>
Co-Authored-By: ict-ql <168183727+ict-ql at users.noreply.github.com>
Co-Authored-By: bdne159 <168184120+bdne159 at users.noreply.github.com>
Co-Authored-By: Zhuke-bosc <168183309+Zhuke-bosc at users.noreply.github.com>
Co-Authored-By: 雷电霸王龙 <111375214+microft11 at users.noreply.github.com>
---
clang/test/Driver/riscv-cpus.c | 37 +++++++++++++++++++++++
clang/test/Misc/target-invalid-cpu-note.c | 4 +--
llvm/lib/Target/RISCV/RISCVProcessors.td | 28 +++++++++++++++++
3 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..54c44a35c3e82e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,40 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknd"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkne"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32x"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl32b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl64b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -76,6 +110,9 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-kunminghu | FileCheck -check-prefix=MTUNE-XIANGSHAN-KUNMINGHU %s
+// MTUNE-XIANGSHAN-KUNMINGHU: "-tune-cpu" "xiangshan-kunminghu"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 21d80b7134508f..a95170aa01abd2 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-kunminghu, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-kunminghu, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index a4a5d9e96c271a..5a5a3bf5033442 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -378,3 +378,31 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs,
+ FeatureStdExtZkn,
+ FeatureStdExtZksed,
+ FeatureStdExtZksh,
+ FeatureStdExtSvinval,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtV,
+ FeatureStdExtZvl128b],
+ [TuneNoDefaultUnroll,
+ TuneZExtHFusion,
+ TuneZExtWFusion,
+ TuneShiftedZExtWFusion]>;
>From d1142a0736ca4f368918485f7748c4279c02990b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=83=9D=E5=BA=B7=E8=BE=BE?= <hebo at bosc.ac.cn>
Date: Sun, 28 Apr 2024 18:19:27 +0800
Subject: [PATCH 2/2] [RISCV] Add scheduling model for XiangShan-KunMingHu
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The "XiangShan" is a high-performance open-source RISC-V processor project, and The "KunMingHu" architecture is its third generation. Official documentation can be found at:[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/).
This Pull Request introduces the foundational scheduling model of the KunMingHu architecture. It encompasses the basic configurations and instruction latencies of the KunMingHu core. Other components will be submitted in subsequent patches.
Co-authored-by:
Chen Jian<chenjian at bosc.ac.cn>
Lv Fang<lvfang at bosc.ac.cn>
Co-Authored-By: Khao7342 <167075369+Khao7342 at users.noreply.github.com>
Co-Authored-By: huxuan0307 <39661208+huxuan0307 at users.noreply.github.com>
Co-Authored-By: Ziyue-Zhang <46214232+Ziyue-Zhang at users.noreply.github.com>
Co-Authored-By: Lin Wang <38717023+MrLinWang at users.noreply.github.com>
Co-Authored-By: ict-ql <168183727+ict-ql at users.noreply.github.com>
Co-Authored-By: bdne159 <168184120+bdne159 at users.noreply.github.com>
Co-Authored-By: Zhuke-bosc <168183309+Zhuke-bosc at users.noreply.github.com>
Co-Authored-By: 雷电霸王龙 <111375214+microft11 at users.noreply.github.com>
---
llvm/lib/Target/RISCV/RISCV.td | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 1489 +++++++++++
.../llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s | 534 ++++
.../llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s | 10 +
.../XiangShan/vector-integer-arithmetic.s | 2271 +++++++++++++++++
6 files changed, 4306 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/vector-integer-arithmetic.s
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 09f496574d64ae..b03a39a3d17502 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -52,6 +52,7 @@ include "RISCVSchedSiFiveP400.td"
include "RISCVSchedSiFiveP600.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedXiangShanNanHu.td"
+include "RISCVSchedXiangShanKunMingHu.td"
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5a5a3bf5033442..6ede6fc21084e4 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -380,7 +380,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneShiftedZExtWFusion]>;
def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
- NoSchedModel,
+ XiangShanKunMingHuModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
new file mode 100644
index 00000000000000..e8460b8bfb05a3
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of Sciences(CAS).
+// The KunMingHu architecture is its third-generation derivative,
+// developed by the Institute of Computing Technology, Chinese Academy of Sciences
+// and the Beijing Institute of Open Source Chip (BOSC),
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===----------------------------------------------------------------------===//
+// KunMingHu core supports "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16<string mx, bit isF = 0, bit isWidening = 0> {
+ defvar t = SchedSEWSet<mx, isF, isWidening>.val;
+ defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+ list<int> val = remove8and16;
+}
+
+class NoZvfhSmallestSEW<string mx, bit isF = 0, bit isWidening = 0> {
+ int r = !head(NoZvfhSchedSEWSet_rm8and16<mx, isF, isWidening>.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
+ list<string> MxList, bit isF = 0,
+ bit isWidening = 0> {
+ if !exists<SchedRead>(name # "_WorstCase") then
+ def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
+ foreach mx = MxList in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF, isWidening>.val in
+ if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
+ def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
+ }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh<string name, int val, list<SchedWrite> writes = []>
+ : NoZvfh_LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1,
+ isWidening=0>;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh<string name, int val, list<SchedWrite> writes = []>
+ : NoZvfh_LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListFW, isF = 1,
+ isWidening=1>;
+
+//===----------------------------------------------------------------------===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 64.
+class NoZvfhSchedSEWSet_rm32and64<string mx, bit isF = 0, bit isWidening = 0> {
+ defvar t = SchedSEWSet<mx, isF, isWidening>.val;
+ defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+ list<int> val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
+ list<string> MxList, bit isF = 0,
+ bit isWidening = 0> {
+ foreach mx = MxList in {
+ foreach sew = NoZvfhSchedSEWSet_rm32and64<mx, isF, isWidening>.val in
+ if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
+ def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
+ }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
+ list<string> MxList, bit isF = 0,
+ bit isWidening = 0> {
+ foreach mx = MxList in {
+ foreach sew = NoZvfhSchedSEWSet_rm32and64<mx, isF, isWidening>.val in
+ if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
+ def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
+ }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF<string name, list<ProcResourceKind> resources>
+ : NoZvfhLMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;
+
+multiclass NoZvfhLMULSEWWriteResFW<string name, list<ProcResourceKind> resources>
+ : NoZvfhLMULSEWWriteResImpl<name, resources, SchedMxListFW, isF=1, isWidening=1>;
+
+multiclass NoZvfhLMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>
+ : NoZvfhLMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
+ : NoZvfhLMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;
+multiclass
+ NoZvfhLMULSEWReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
+ : NoZvfhLMULSEWReadAdvanceImpl<name, val, writes, SchedMxListFW, isF=1,
+ isWidening = 1>;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSgnjV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSgnjF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFCvtIToFV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWCvtFToFV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFNCvtIToFV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFNCvtFToFV", []>;
+
+// 14. Vector Reduction Operations
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRedV_From", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRedOV_From", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>;
+defm "" : NoZvfhLMULSEWWriteResFWRed<"WriteVFWRedV_From", []>;
+defm "" : NoZvfhLMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>;
+
+// Read
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : NoZvfhLMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+} // Unsupported
+} // UnsupportedSchedZvfh
+
+//===----------------------------------------------------------------------===//
+
+class XSGetCyclesVIALU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 2,
+ !eq(mx, "M2") : 4,
+ !eq(mx, "M4") : 8,
+ !eq(mx, "M8") : 16,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 2,
+ !eq(mx, "MF8") : 2
+ );
+}
+
+class XSGetCyclesVIMAC<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 3,
+ !eq(mx, "M2") : 6,
+ !eq(mx, "M4") : 12,
+ !eq(mx, "M8") : 24,
+ !eq(mx, "MF2") : 3,
+ !eq(mx, "MF4") : 3,
+ !eq(mx, "MF8") : 3
+ );
+}
+
+class XSGetCyclesVIDIV<string mx, int sew> {
+ int uop = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+ int cycles = !cond(
+ !eq(sew, 64) : 19, // I64: 4-19
+ !eq(sew, 32) : 11, // I32: 4-11
+ !eq(sew, 16) : 7, // I16: 4-7
+ !eq(sew, 8) : 6 // I8: 6
+ );
+ int c = !mul(uop, cycles);
+}
+
+class XSGetCyclesVIPU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 2,
+ !eq(mx, "M2") : 4,
+ !eq(mx, "M4") : 8,
+ !eq(mx, "M8") : 16,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 2,
+ !eq(mx, "MF8") : 2
+ );
+}
+
+class XSGetCyclesVPPU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 2,
+ !eq(mx, "M2") : 4,
+ !eq(mx, "M4") : 8,
+ !eq(mx, "M8") : 16,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 2,
+ !eq(mx, "MF8") : 2
+ );
+}
+
+class XSGetCyclesVFALU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 2,
+ !eq(mx, "M2") : 4,
+ !eq(mx, "M4") : 8,
+ !eq(mx, "M8") : 16,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 2,
+ !eq(mx, "MF8") : 2
+ );
+}
+
+class XSGetCyclesVFMA<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 4,
+ !eq(mx, "M2") : 8,
+ !eq(mx, "M4") : 16,
+ !eq(mx, "M8") : 32,
+ !eq(mx, "MF2") : 4,
+ !eq(mx, "MF4") : 4,
+ !eq(mx, "MF8") : 4
+ );
+}
+
+class XSGetCyclesVFDIV<string mx, int sew> {
+ assert !or(!eq(sew, 32), !eq(sew, 64)), "Floating-point SEW of KunMingHu can only be 32 or 64.";
+ int uop = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+ int cycles = !cond(
+ !eq(sew, 64) : 15, // FP64: 15
+ !eq(sew, 32) : 10, // FP32: 10
+ );
+ int c = !mul(uop, cycles);
+}
+
+class XSGetCyclesVFCVT<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 3,
+ !eq(mx, "M2") : 6,
+ !eq(mx, "M4") : 12,
+ !eq(mx, "M8") : 24,
+ !eq(mx, "MF2") : 3,
+ !eq(mx, "MF4") : 3,
+ !eq(mx, "MF8") : 3
+ );
+}
+
+class XSGetCyclesVLDU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 8,
+ !eq(mx, "M2") : 16,
+ !eq(mx, "M4") : 32,
+ !eq(mx, "M8") : 64,
+ !eq(mx, "MF2") : 8,
+ !eq(mx, "MF4") : 8,
+ !eq(mx, "MF8") : 8
+ );
+}
+
+class XSGetCyclesVSTU<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 7,
+ !eq(mx, "M2") : 14,
+ !eq(mx, "M4") : 28,
+ !eq(mx, "M8") : 56,
+ !eq(mx, "MF2") : 7,
+ !eq(mx, "MF4") : 7,
+ !eq(mx, "MF8") : 7
+ );
+}
+
+// If mx is the maximum LMUL in the MxList, then c is true, indicating the worst case.
+class XSIsWorstCaseMX<string mx, list<string> MxList> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+// If mx is the maximum LMUL in the MxList, and sew is the minimum value
+// when LMUL=mx, then c is true, indicating the worst case.
+class XSIsWorstCaseMXSEW<string mx, int sew, list<string> MxList,
+ bit isF = 0> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ defvar SSEW = NoZvfhSmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class XSLDUtoAnyBypass<SchedRead read, int cycles = 2>
+ : ReadAdvance<read, cycles, [WriteLDB, WriteLDH,
+ WriteLDW, WriteLDD,
+ WriteAtomicW, WriteAtomicD,
+ WriteAtomicLDW, WriteAtomicLDD]>;
+
+//===----------------------------------------------------------------------===//
+
+def XiangShanKunMingHuModel : SchedMachineModel {
+ let IssueWidth = 6; // 6-way decode and dispatch
+ let MicroOpBufferSize = 256;
+ let LoopMicroOpBufferSize = 48; // Instruction queue size
+ let LoadLatency = 6;
+ let MispredictPenalty = 13; // Based on estimate of pipeline depth.
+ let PostRAScheduler = 1;
+ let CompleteModel = 0;
+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr];
+}
+
+let SchedModel = XiangShanKunMingHuModel in {
+// Define each kind of processor resource and number available.
+/// Pipline
+let BufferSize = 12 in {
+ // Integer
+ def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU2 : ProcResource<1>; // ALU
+ def XSPipeALU3 : ProcResource<1>; // ALU
+ def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSET, CSR, FENCE
+ def XSPipeDIV : ProcResource<1>; // DIV
+
+ // Vector and floating-point
+ def XSPipVFEX0 : ProcResource<1>; // VFALU, VFMA, VIALU, VIMAC
+ def XSPipVFEX1 : ProcResource<1>; // VIPU, VPPU, VFCVT, F2V, VSET2
+ def XSPipVFEX2 : ProcResource<1>; // VFALU, VFMA, VIALU
+ def XSPipVFEX3 : ProcResource<1>; // VFDIV, VIDIV
+
+ // Vector load and store
+ def XSPipVLDU : ProcResource<1>; // VLDU
+ def XSPipVSTU : ProcResource<1>; // VSTU
+}
+
+let BufferSize = 24 in {
+ // Load and store
+ def XSPipeLDU0 : ProcResource<1>; // LDU
+ def XSPipeLDU1 : ProcResource<1>; // LDU
+ def XSPipeLDU2 : ProcResource<1>; // LDU
+ def XSPipeSTU0 : ProcResource<1>; // STU
+ def XSPipeSTU1 : ProcResource<1>; // STU
+}
+
+def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3]>;
+def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+def XSPipeGroupJMP : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+
+def XSPipeGroupVIALU : ProcResGroup<[XSPipVFEX0, XSPipVFEX2]>;
+def XSPipeGroupVFALU : ProcResGroup<[XSPipVFEX0, XSPipVFEX2]>;
+def XSPipeGroupVFMA : ProcResGroup<[XSPipVFEX0, XSPipVFEX2]>;
+
+def XSPipeGroupLDU : ProcResGroup<[XSPipeLDU0, XSPipeLDU1, XSPipeLDU2]>;
+def XSPipeGroupSTU : ProcResGroup<[XSPipeSTU0, XSPipeSTU1]>;
+
+/// Register
+def XS_INT_PRF : RegisterFile<224, [GPR], [1], [1], 0, 0>;
+def XS_FP_PRF : RegisterFile<192, [FPR64], [1], [1], 0, 0>;
+
+//===----------------------------------------------------------------------===//
+
+// Jump
+let Latency = 1 in {
+ def : WriteRes<WriteJmp, [XSPipeGroupBRU]>;
+ def : WriteRes<WriteJal, [XSPipeGroupJMP]>;
+ def : WriteRes<WriteJalr, [XSPipeGroupJMP]>;
+}
+
+// Integer arithmetic and logic
+let Latency = 1 in {
+ def : WriteRes<WriteIALU32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteIALU, [XSPipeGroupALU]>;
+ def : WriteRes<WriteShiftImm32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteShiftImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteShiftReg32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteShiftReg, [XSPipeGroupALU]>;
+}
+
+// Integer multiplication
+let Latency = 3 in {
+ def : WriteRes<WriteIMul, [XSPipeGroupMUL]>;
+ def : WriteRes<WriteIMul32, [XSPipeGroupMUL]>;
+}
+
+// Integer division
+// Worst case latency is used.
+// The latency of integer division ranges from 4 to 20.
+let Latency = 20, ReleaseAtCycles = [20] in {
+ def : WriteRes<WriteIDiv32, [XSPipeDIV]>;
+ def : WriteRes<WriteIDiv, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem32, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem, [XSPipeDIV]>;
+}
+
+// Memory
+let Latency = 5 in {
+ def : WriteRes<WriteSTB, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTH, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTD, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST32, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST64, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTD, [XSPipeGroupSTU]>;
+}
+let Latency = 6 in {
+ def : WriteRes<WriteLDB, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteLDH, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteLDW, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteLDD, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteFLD32, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteFLD64, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteAtomicW, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteAtomicD, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteAtomicLDW, [XSPipeGroupLDU]>;
+ def : WriteRes<WriteAtomicLDD, [XSPipeGroupLDU]>;
+}
+
+let Latency = 2 in {
+ def : WriteRes<WriteFAdd32, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFAdd64, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFCmp32, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFCmp64, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFMinMax32, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFMinMax64, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFClass32, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFClass64, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFSGNJ32, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteFSGNJ64, [XSPipeGroupVFALU]>;
+}
+
+let Latency = 4 in {
+ def : WriteRes<WriteFMul32, [XSPipeGroupVFMA]>;
+ def : WriteRes<WriteFMul64, [XSPipeGroupVFMA]>;
+ def : WriteRes<WriteFMA32, [XSPipeGroupVFMA]>;
+ def : WriteRes<WriteFMA64, [XSPipeGroupVFMA]>;
+}
+
+// VFDIV
+let Latency = 10 in {
+ def : WriteRes<WriteFDiv32, [XSPipVFEX3]>;
+ def : WriteRes<WriteFSqrt32, [XSPipVFEX3]>;
+}
+let Latency = 15 in {
+ def : WriteRes<WriteFDiv64, [XSPipVFEX3]>;
+ def : WriteRes<WriteFSqrt64, [XSPipVFEX3]>;
+}
+
+// VFCVT
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtF32ToI32, [XSPipVFEX1]>;
+ def : WriteRes<WriteFCvtF32ToI64, [XSPipVFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI32, [XSPipVFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI64, [XSPipVFEX1]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipVFEX1]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipVFEX1]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipVFEX1]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipVFEX1]>;
+}
+
+// I2V
+let Latency = 1 in {
+ def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
+}
+
+// I2F
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF64, [XSPipeBJU2]>;
+}
+
+/// Zb*
+let Latency = 1 in {
+ // Zba
+ def : WriteRes<WriteSHXADD, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSHXADD32, [XSPipeGroupALU]>;
+
+ // Zbb
+ def : WriteRes<WriteRotateImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateImm32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WriteORCB, [XSPipeGroupALU]>;
+ def : WriteRes<WriteIMinMax, [XSPipeGroupALU]>;
+
+ // Zbs
+ def : WriteRes<WriteSingleBit, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSingleBitImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXT, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXTI, [XSPipeGroupALU]>;
+
+ // Zbkb
+ def : WriteRes<WriteBREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
+}
+
+let Latency = 3 in {
+ // Zbb
+ def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP32, [XSPipeGroupBKU]>;
+
+ // Zbc
+ def : WriteRes<WriteCLMUL, [XSPipeGroupBKU]>;
+
+ // Zbkx
+ def : WriteRes<WriteXPERM, [XSPipeGroupBKU]>;
+}
+
+/// Vector extension
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, [XSPipeGroupALU]>;
+
+// 6. Configuration-Setting Instructions
+// VSET VSET2
+let Latency = 1 in {
+ def : WriteRes<WriteVSETVLI, [XSPipVFEX1]>;
+ def : WriteRes<WriteVSETIVLI, [XSPipVFEX1]>;
+ def : WriteRes<WriteVSETVL, [XSPipeBJU2]>;
+}
+
+// 7. Vector Loads and Stores
+// VLDU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVLDU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDM", [XSPipVLDU], mx, IsWorstCase>;
+ }
+}
+
+// VSTU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVSTU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVSTE", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [XSPipVSTU], mx, IsWorstCase>;
+ }
+}
+
+// VLDU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVLDU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDS8", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS16", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS32", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS64", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [XSPipVLDU], mx, IsWorstCase>;
+ }
+}
+
+// VSTU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVSTU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVSTS8", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS16", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS32", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS64", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [XSPipVSTU], mx, IsWorstCase>;
+ }
+}
+
+// VLDU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVLDU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDFF", [XSPipVLDU], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar CyclesLoad = XSGetCyclesVLDU<mx>.c;
+ defvar CyclesStore = XSGetCyclesVSTU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = CyclesLoad in {
+ // VLDU
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [XSPipVLDU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [XSPipVLDU], mx, IsWorstCase>;
+ }
+ let Latency = CyclesStore in {
+ // VSTU
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [XSPipVSTU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [XSPipVSTU], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// VLDU
+let Latency = 8 in
+ def : WriteRes<WriteVLD1R, [XSPipVLDU]>;
+let Latency = 16 in
+ def : WriteRes<WriteVLD2R, [XSPipVLDU]>;
+let Latency = 32 in
+ def : WriteRes<WriteVLD4R, [XSPipVLDU]>;
+let Latency = 64 in
+ def : WriteRes<WriteVLD8R, [XSPipVLDU]>;
+
+// VSTU
+let Latency = 7 in
+ def : WriteRes<WriteVST1R, [XSPipVSTU]>;
+let Latency = 14 in
+ def : WriteRes<WriteVST2R, [XSPipVSTU]>;
+let Latency = 28 in
+ def : WriteRes<WriteVST4R, [XSPipVSTU]>;
+let Latency = 56 in
+ def : WriteRes<WriteVST8R, [XSPipVSTU]>;
+
+// 11. Vector Integer Arithmetic Instructions
+// VIALU
+// The latency of KunMingHu vector extension instructions is independent of SEW.
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVExtV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+
+ // Because .vx and .vi need to be converted to .vv before execution,
+ // an additional cycle is required.
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIALUX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+}
+
+// VIALU
+foreach mx = SchedMxListW in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+
+ }
+}
+
+// VIMAC
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIMAC<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIMulV", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIMulX", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+}
+
+// VIDIV
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = XSGetCyclesVIDIV<mx, sew>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [XSPipVFEX3], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [XSPipVFEX3], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VIMAC
+foreach mx = SchedMxListW in {
+ defvar Cycles = XSGetCyclesVIMAC<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [XSPipVFEX0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [XSPipVFEX0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+}
+
+// VIMAC
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIMAC<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+}
+
+// VIALU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+
+ // 12. Vector Fixed-Point Arithmetic Instructions
+ defm "" : LMULWriteResMX<"WriteVSALUX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+}
+
+// VIMAC
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIMAC<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVSMulV", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVSMulX", [XSPipVFEX0], mx, IsWorstCase>;
+ }
+}
+
+// VIALU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+}
+
+// VIALU
+foreach mx = SchedMxListW in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVNClipV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVNClipX", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+}
+
+// 13. Vector Floating-Point Instructions
+// VFALU
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFALU
+foreach mx = SchedMxListFW in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFMA
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFMA<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFDIV
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFDIV<mx, sew>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [XSPipVFEX3], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [XSPipVFEX3], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFMA
+foreach mx = SchedMxListFW in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFMA<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFMA
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFMA<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFMA
+foreach mx = SchedMxListFW in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFMA<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [XSPipeGroupVFMA], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFDIV
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFDIV<mx, sew>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [XSPipVFEX3], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFALU
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFALU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [XSPipeGroupVFALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFClassV", [XSPipeGroupVFALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [XSPipeGroupVFALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [XSPipeGroupVFALU], mx, IsWorstCase>;
+ }
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [XSPipeGroupVFALU], mx, IsWorstCase>;
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListFW in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxListFW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListFW in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFCVT
+foreach mx = SchedMxListW in {
+ defvar Cycles = XSGetCyclesVFCVT<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// 14. Vector Reduction Operations
+// VIPU
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = XSGetCyclesVIPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VIPU
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVIPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFALU
+foreach mx = SchedMxListF in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=0>.val in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VFALU
+foreach mx = SchedMxListFWRed in {
+ foreach sew = NoZvfhSchedSEWSet_rm8and16<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = XSGetCyclesVFALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, isF=1>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [XSPipeGroupVFALU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 15. Vector Mask Instructions
+// VIALU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIALU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [XSPipeGroupVIALU], mx, IsWorstCase>;
+ }
+}
+
+// VIPU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVIPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVMPopV", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIotaV", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// 16. Vector Permutation Instructions
+let Latency = 2 in {
+ // VIALU
+ def : WriteRes<WriteVMovSX, [XSPipVFEX0]>;
+ // VIPU
+ def : WriteRes<WriteVMovXS, [XSPipVFEX1]>;
+}
+
+// VFALU
+let Latency = 2 in {
+ def : WriteRes<WriteVMovSF, [XSPipeGroupVFALU]>;
+ def : WriteRes<WriteVMovFS, [XSPipeGroupVFALU]>;
+}
+
+// VPPU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVPPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVISlideX", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideI", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// VPPU
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = XSGetCyclesVPPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VPPU
+foreach mx = SchedMxList in {
+ defvar Cycles = XSGetCyclesVPPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(Cycles, 1) in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [XSPipVFEX1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [XSPipVFEX1], mx, IsWorstCase>;
+ }
+}
+
+// VPPU
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = XSGetCyclesVPPU<mx>.c;
+ defvar IsWorstCase = XSIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [XSPipVFEX1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// VPPU
+let Latency = 2 in
+ def : WriteRes<WriteVMov1V, [XSPipVFEX1]>;
+let Latency = 4 in
+ def : WriteRes<WriteVMov2V, [XSPipVFEX1]>;
+let Latency = 6 in
+ def : WriteRes<WriteVMov4V, [XSPipVFEX1]>;
+let Latency = 8 in
+ def : WriteRes<WriteVMov8V, [XSPipVFEX1]>;
+
+// Others
+def : WriteRes<WriteCSR, [XSPipeBJU2]>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : XSLDUtoAnyBypass<ReadIALU>;
+def : XSLDUtoAnyBypass<ReadIALU32>;
+def : XSLDUtoAnyBypass<ReadShiftImm>;
+def : XSLDUtoAnyBypass<ReadShiftImm32>;
+def : XSLDUtoAnyBypass<ReadShiftReg>;
+def : XSLDUtoAnyBypass<ReadShiftReg32>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+/// B extension
+// Zba
+def : XSLDUtoAnyBypass<ReadSHXADD>;
+def : XSLDUtoAnyBypass<ReadSHXADD32>;
+// Zbb
+def : XSLDUtoAnyBypass<ReadRotateImm>;
+def : XSLDUtoAnyBypass<ReadRotateImm32>;
+def : XSLDUtoAnyBypass<ReadRotateReg>;
+def : XSLDUtoAnyBypass<ReadRotateReg32>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : XSLDUtoAnyBypass<ReadREV8>;
+def : XSLDUtoAnyBypass<ReadORCB>;
+def : XSLDUtoAnyBypass<ReadIMinMax>;
+// Zbc
+def : ReadAdvance<ReadCLMUL, 0>;
+// Zbs
+def : XSLDUtoAnyBypass<ReadSingleBit>;
+def : XSLDUtoAnyBypass<ReadSingleBitImm>;
+// Zbkb
+def : XSLDUtoAnyBypass<ReadBREV8>;
+def : XSLDUtoAnyBypass<ReadPACK>;
+def : XSLDUtoAnyBypass<ReadPACK32>;
+def : XSLDUtoAnyBypass<ReadZIP>;
+// Zbkx
+def : ReadAdvance<ReadXPERM, 0>;
+
+/// V extension
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// These are already LMUL aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 11. Vector Integer Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVIALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVIALUX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVExtV", 0>;
+defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 13. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFRecpV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceFnoZvfh<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFWnoZvfh<"ReadVFNCvtFToFV", 0>;
+
+// 14. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFRedMinMaxV, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 16. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// These are already LMUL aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVMergeOp_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
+}
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedZfa;
+defm : UnsupportedSchedZfh;
+defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedZvfh;
+
+// Move Elimination
+def : IsOptimizableRegisterMove<[
+ InstructionEquivalenceClass<[C_MV], TruePred >
+]>;
+
+} // SchedModel
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s
new file mode 100644
index 00000000000000..3f4047bc019369
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s
@@ -0,0 +1,534 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline \
+# RUN: -timeline-max-cycles=1000 -iterations=1 < %s | FileCheck %s
+
+lui a0, 1
+auipc a1, 1
+add a0, a0, a1
+addi a0, a0, 1
+addw a0, a0, a0
+addiw a0, a0, 1
+sub a0, a0, a0
+subw a0, a0, a0
+and a0, a0, a0
+andi a0, a0, 1
+or a0, a0, a0
+ori a0, a0, 1
+xor a0, a0, a0
+xori a0, a0, 1
+sll a0, a0, a0
+slli a0, a0, 1
+sllw a0, a0, a0
+slliw a0, a0, 1
+srl a0, a0, a0
+srli a0, a0, 1
+srlw a0, a0, a0
+srliw a0, a0, 1
+sra a0, a0, a0
+srai a0, a0, 1
+sraw a0, a0, a0
+sraiw a0, a0, 1
+slt a0, a0, a0
+slti a0, a0, 1
+sltu a0, a0, a0
+sltiu a0, a0, 1
+mul a0, a0, a0
+add a0, a0, a0
+mulw a0, a0, a0
+add a0, a0, a0
+beq a0, a0, 1f
+1:
+add a0, a0, a0
+bne a0, a0, 1f
+1:
+add a0, a0, a0
+blt a0, a0, 1f
+1:
+add a0, a0, a0
+bltu a0, a0, 1f
+1:
+add a0, a0, a0
+bge a0, a0, 1f
+1:
+add a0, a0, a0
+bgeu a0, a0, 1f
+1:
+# zba
+add.uw a0, a0, a0
+slli.uw a0, a0, 1
+sh1add.uw a0, a0, a0
+sh2add.uw a0, a0, a0
+sh3add.uw a0, a0, a0
+sh1add a0, a0, a0
+sh2add a0, a0, a0
+sh3add a0, a0, a0
+# zbb
+andn a0, a0, a0
+orn a0, a0, a0
+xnor a0, a0, a0
+sext.b a0, a0
+sext.h a0, a0
+zext.h a0, a0
+min a0, a0, a0
+minu a0, a0, a0
+max a0, a0, a0
+maxu a0, a0, a0
+rol a0, a0, a0
+ror a0, a0, a0
+rori a0, a0, 1
+clz a0, a0
+clzw a0, a0
+ctz a0, a0
+ctzw a0, a0
+cpop a0, a0
+add a0, a0, a0
+cpopw a0, a0
+add a0, a0, a0
+rev8 a0, a0
+orc.b a0, a0
+lb a0, 0(a0)
+add a0, a0, a0
+lh a0, 0(a0)
+and a0, a0, a0
+lw a0, 0(a0)
+or a0, a0, a0
+ld a0, 0(a0)
+xor a0, a0, a0
+lbu a0, 0(a0)
+addi a0, a0, 1
+lhu a0, 0(a0)
+sub a0, a0, a0
+lwu a0, 0(a0)
+addw a0, a0, a0
+jr a0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 91
+# CHECK-NEXT: Total Cycles: 124
+# CHECK-NEXT: Total uOps: 91
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.73
+# CHECK-NEXT: IPC: 0.73
+# CHECK-NEXT: Block RThroughput: 17.3
+
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 lui a0, 1
+# CHECK-NEXT: 1 1 0.25 auipc a1, 1
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 subw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 and a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 or a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 seqz a0, a0
+# CHECK-NEXT: 1 3 0.50 mul a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 mulw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 beq a0, a0, .Ltmp0
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 bne a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 blt a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 bltu a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 bge a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 bgeu a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 0.25 add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 slli.uw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sh1add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sh2add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sh3add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 xnor a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 sext.b a0, a0
+# CHECK-NEXT: 1 1 0.25 sext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 zext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 min a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 max a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 rori a0, a0, 1
+# CHECK-NEXT: 1 3 0.50 clz a0, a0
+# CHECK-NEXT: 1 3 0.50 clzw a0, a0
+# CHECK-NEXT: 1 3 0.50 ctz a0, a0
+# CHECK-NEXT: 1 3 0.50 ctzw a0, a0
+# CHECK-NEXT: 1 3 0.50 cpop a0, a0
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 cpopw a0, a0
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 rev8 a0, a0
+# CHECK-NEXT: 1 1 0.25 orc.b a0, a0
+# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a0
+# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 and a0, a0, a0
+# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 or a0, a0, a0
+# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 xor a0, a0, a0
+# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 addi a0, a0, 1
+# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 sub a0, a0, a0
+# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a0)
+# CHECK-NEXT: 1 1 0.25 addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 jr a0
+
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipVFEX0
+# CHECK-NEXT: [1] - XSPipVFEX1
+# CHECK-NEXT: [2] - XSPipVFEX2
+# CHECK-NEXT: [3] - XSPipVFEX3
+# CHECK-NEXT: [4] - XSPipVLDU
+# CHECK-NEXT: [5] - XSPipVSTU
+# CHECK-NEXT: [6] - XSPipeALU0
+# CHECK-NEXT: [7] - XSPipeALU1
+# CHECK-NEXT: [8] - XSPipeALU2
+# CHECK-NEXT: [9] - XSPipeALU3
+# CHECK-NEXT: [10] - XSPipeBJU0
+# CHECK-NEXT: [11] - XSPipeBJU1
+# CHECK-NEXT: [12] - XSPipeBJU2
+# CHECK-NEXT: [13] - XSPipeDIV
+# CHECK-NEXT: [14] - XSPipeLDU0
+# CHECK-NEXT: [15] - XSPipeLDU1
+# CHECK-NEXT: [16] - XSPipeLDU2
+# CHECK-NEXT: [17] - XSPipeSTU0
+# CHECK-NEXT: [18] - XSPipeSTU1
+
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
+# CHECK-NEXT: - - - - - - 20.00 20.00 18.00 19.00 2.00 2.00 3.00 - 2.00 2.00 3.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] Instructions:
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - lui a0, 1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - auipc a1, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - add a0, a0, a1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - and a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - or a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - xor a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sll a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sllw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sra a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sraw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - slt a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sltu a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - seqz a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - beq a0, a0, .Ltmp0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - bne a0, a0, .Ltmp1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - blt a0, a0, .Ltmp2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - bltu a0, a0, .Ltmp3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - bge a0, a0, .Ltmp4
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - bgeu a0, a0, .Ltmp5
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - add.uw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - slli.uw a0, a0, 1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - sh2add a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sh3add a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - andn a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - orn a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - xnor a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - sext.b a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - sext.h a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - zext.h a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - min a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - minu a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - max a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - maxu a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - ror a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - rori a0, a0, 1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - clz a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - clzw a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - ctz a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - ctzw a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - cpop a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - cpopw a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - rev8 a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - orc.b a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - lb a0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - lh a0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - and a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - lw a0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - or a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - ld a0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - xor a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - lbu a0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - lwu a0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - jr a0
+
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123
+
+# CHECK: [0,0] DeER . . . . . . . . . . . . . . . . . . . . . . . . . lui a0, 1
+# CHECK-NEXT: [0,1] DeER . . . . . . . . . . . . . . . . . . . . . . . . . auipc a1, 1
+# CHECK-NEXT: [0,2] D=eER. . . . . . . . . . . . . . . . . . . . . . . . . add a0, a0, a1
+# CHECK-NEXT: [0,3] D==eER . . . . . . . . . . . . . . . . . . . . . . . . addi a0, a0, 1
+# CHECK-NEXT: [0,4] D===eER . . . . . . . . . . . . . . . . . . . . . . . . addw a0, a0, a0
+# CHECK-NEXT: [0,5] D====eER . . . . . . . . . . . . . . . . . . . . . . . . addiw a0, a0, 1
+# CHECK-NEXT: [0,6] .D====eER . . . . . . . . . . . . . . . . . . . . . . . . sub a0, a0, a0
+# CHECK-NEXT: [0,7] .D=====eER. . . . . . . . . . . . . . . . . . . . . . . . subw a0, a0, a0
+# CHECK-NEXT: [0,8] .D======eER . . . . . . . . . . . . . . . . . . . . . . . and a0, a0, a0
+# CHECK-NEXT: [0,9] .D=======eER . . . . . . . . . . . . . . . . . . . . . . . andi a0, a0, 1
+# CHECK-NEXT: [0,10] .D========eER . . . . . . . . . . . . . . . . . . . . . . . or a0, a0, a0
+# CHECK-NEXT: [0,11] .D=========eER . . . . . . . . . . . . . . . . . . . . . . . ori a0, a0, 1
+# CHECK-NEXT: [0,12] . D=========eER. . . . . . . . . . . . . . . . . . . . . . . xor a0, a0, a0
+# CHECK-NEXT: [0,13] . D==========eER . . . . . . . . . . . . . . . . . . . . . . xori a0, a0, 1
+# CHECK-NEXT: [0,14] . D===========eER . . . . . . . . . . . . . . . . . . . . . . sll a0, a0, a0
+# CHECK-NEXT: [0,15] . D============eER . . . . . . . . . . . . . . . . . . . . . . slli a0, a0, 1
+# CHECK-NEXT: [0,16] . D=============eER . . . . . . . . . . . . . . . . . . . . . . sllw a0, a0, a0
+# CHECK-NEXT: [0,17] . D==============eER. . . . . . . . . . . . . . . . . . . . . . slliw a0, a0, 1
+# CHECK-NEXT: [0,18] . D==============eER . . . . . . . . . . . . . . . . . . . . . srl a0, a0, a0
+# CHECK-NEXT: [0,19] . D===============eER . . . . . . . . . . . . . . . . . . . . . srli a0, a0, 1
+# CHECK-NEXT: [0,20] . D================eER . . . . . . . . . . . . . . . . . . . . . srlw a0, a0, a0
+# CHECK-NEXT: [0,21] . D=================eER . . . . . . . . . . . . . . . . . . . . . srliw a0, a0, 1
+# CHECK-NEXT: [0,22] . D==================eER. . . . . . . . . . . . . . . . . . . . . sra a0, a0, a0
+# CHECK-NEXT: [0,23] . D===================eER . . . . . . . . . . . . . . . . . . . . srai a0, a0, 1
+# CHECK-NEXT: [0,24] . D===================eER . . . . . . . . . . . . . . . . . . . . sraw a0, a0, a0
+# CHECK-NEXT: [0,25] . D====================eER . . . . . . . . . . . . . . . . . . . . sraiw a0, a0, 1
+# CHECK-NEXT: [0,26] . D=====================eER . . . . . . . . . . . . . . . . . . . . slt a0, a0, a0
+# CHECK-NEXT: [0,27] . D======================eER. . . . . . . . . . . . . . . . . . . . slti a0, a0, 1
+# CHECK-NEXT: [0,28] . D=======================eER . . . . . . . . . . . . . . . . . . . sltu a0, a0, a0
+# CHECK-NEXT: [0,29] . D========================eER . . . . . . . . . . . . . . . . . . . seqz a0, a0
+# CHECK-NEXT: [0,30] . D========================eeeER. . . . . . . . . . . . . . . . . . . mul a0, a0, a0
+# CHECK-NEXT: [0,31] . D===========================eER . . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,32] . D============================eeeER . . . . . . . . . . . . . . . . . . mulw a0, a0, a0
+# CHECK-NEXT: [0,33] . D===============================eER. . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,34] . D================================eER . . . . . . . . . . . . . . . . . beq a0, a0, .Ltmp0
+# CHECK-NEXT: [0,35] . D================================eER . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,36] . .D================================eER . . . . . . . . . . . . . . . . . bne a0, a0, .Ltmp1
+# CHECK-NEXT: [0,37] . .D================================eER . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,38] . .D=================================eER . . . . . . . . . . . . . . . . . blt a0, a0, .Ltmp2
+# CHECK-NEXT: [0,39] . .D=================================eER . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,40] . .D==================================eER . . . . . . . . . . . . . . . . . bltu a0, a0, .Ltmp3
+# CHECK-NEXT: [0,41] . .D==================================eER . . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,42] . . D==================================eER. . . . . . . . . . . . . . . . . bge a0, a0, .Ltmp4
+# CHECK-NEXT: [0,43] . . D==================================eER. . . . . . . . . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,44] . . D===================================eER . . . . . . . . . . . . . . . . bgeu a0, a0, .Ltmp5
+# CHECK-NEXT: [0,45] . . D===================================eER . . . . . . . . . . . . . . . . add.uw a0, a0, a0
+# CHECK-NEXT: [0,46] . . D====================================eER . . . . . . . . . . . . . . . . slli.uw a0, a0, 1
+# CHECK-NEXT: [0,47] . . D=====================================eER . . . . . . . . . . . . . . . . sh1add.uw a0, a0, a0
+# CHECK-NEXT: [0,48] . . D=====================================eER . . . . . . . . . . . . . . . . sh2add.uw a0, a0, a0
+# CHECK-NEXT: [0,49] . . D======================================eER. . . . . . . . . . . . . . . . sh3add.uw a0, a0, a0
+# CHECK-NEXT: [0,50] . . D=======================================eER . . . . . . . . . . . . . . . sh1add a0, a0, a0
+# CHECK-NEXT: [0,51] . . D========================================eER . . . . . . . . . . . . . . . sh2add a0, a0, a0
+# CHECK-NEXT: [0,52] . . D=========================================eER . . . . . . . . . . . . . . . sh3add a0, a0, a0
+# CHECK-NEXT: [0,53] . . D==========================================eER . . . . . . . . . . . . . . . andn a0, a0, a0
+# CHECK-NEXT: [0,54] . . D==========================================eER. . . . . . . . . . . . . . . orn a0, a0, a0
+# CHECK-NEXT: [0,55] . . D===========================================eER . . . . . . . . . . . . . . xnor a0, a0, a0
+# CHECK-NEXT: [0,56] . . D============================================eER . . . . . . . . . . . . . . sext.b a0, a0
+# CHECK-NEXT: [0,57] . . D=============================================eER . . . . . . . . . . . . . . sext.h a0, a0
+# CHECK-NEXT: [0,58] . . D==============================================eER . . . . . . . . . . . . . . zext.h a0, a0
+# CHECK-NEXT: [0,59] . . D===============================================eER. . . . . . . . . . . . . . min a0, a0, a0
+# CHECK-NEXT: [0,60] . . D===============================================eER . . . . . . . . . . . . . minu a0, a0, a0
+# CHECK-NEXT: [0,61] . . D================================================eER . . . . . . . . . . . . . max a0, a0, a0
+# CHECK-NEXT: [0,62] . . D=================================================eER . . . . . . . . . . . . . maxu a0, a0, a0
+# CHECK-NEXT: [0,63] . . D==================================================eER . . . . . . . . . . . . . rol a0, a0, a0
+# CHECK-NEXT: [0,64] . . D===================================================eER. . . . . . . . . . . . . ror a0, a0, a0
+# CHECK-NEXT: [0,65] . . D====================================================eER . . . . . . . . . . . . rori a0, a0, 1
+# CHECK-NEXT: [0,66] . . .D====================================================eeeER . . . . . . . . . . . . clz a0, a0
+# CHECK-NEXT: [0,67] . . .D=======================================================eeeER . . . . . . . . . . . clzw a0, a0
+# CHECK-NEXT: [0,68] . . .D==========================================================eeeER. . . . . . . . . . . ctz a0, a0
+# CHECK-NEXT: [0,69] . . .D=============================================================eeeER . . . . . . . . . . ctzw a0, a0
+# CHECK-NEXT: [0,70] . . .D================================================================eeeER . . . . . . . . . cpop a0, a0
+# CHECK-NEXT: [0,71] . . .D===================================================================eER . . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,72] . . . D===================================================================eeeER. . . . . . . . . cpopw a0, a0
+# CHECK-NEXT: [0,73] . . . D======================================================================eER . . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,74] . . . D=======================================================================eER . . . . . . . . rev8 a0, a0
+# CHECK-NEXT: [0,75] . . . D========================================================================eER . . . . . . . . orc.b a0, a0
+# CHECK-NEXT: [0,76] . . . D=========================================================================eeeeeeER . . . . . . . lb a0, 0(a0)
+# CHECK-NEXT: [0,77] . . . D=============================================================================eE-R . . . . . . . add a0, a0, a0
+# CHECK-NEXT: [0,78] . . . D=============================================================================eeeeeeER . . . . . . lh a0, 0(a0)
+# CHECK-NEXT: [0,79] . . . D=================================================================================eE-R . . . . . . and a0, a0, a0
+# CHECK-NEXT: [0,80] . . . D==================================================================================eeeeeeER . . . . . lw a0, 0(a0)
+# CHECK-NEXT: [0,81] . . . D======================================================================================eE-R . . . . . or a0, a0, a0
+# CHECK-NEXT: [0,82] . . . D=======================================================================================eeeeeeER . . . . ld a0, 0(a0)
+# CHECK-NEXT: [0,83] . . . D===========================================================================================eE-R . . . . xor a0, a0, a0
+# CHECK-NEXT: [0,84] . . . D===========================================================================================eeeeeeER . . . lbu a0, 0(a0)
+# CHECK-NEXT: [0,85] . . . D===============================================================================================eE-R . . . addi a0, a0, 1
+# CHECK-NEXT: [0,86] . . . D================================================================================================eeeeeeER . . lhu a0, 0(a0)
+# CHECK-NEXT: [0,87] . . . D====================================================================================================eE-R . . sub a0, a0, a0
+# CHECK-NEXT: [0,88] . . . D=====================================================================================================eeeeeeER lwu a0, 0(a0)
+# CHECK-NEXT: [0,89] . . . D=========================================================================================================eE-R addw a0, a0, a0
+# CHECK-NEXT: [0,90] . . . D=========================================================================================================eER jr a0
+
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 lui a0, 1
+# CHECK-NEXT: 1. 1 1.0 1.0 0.0 auipc a1, 1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 add a0, a0, a1
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 addi a0, a0, 1
+# CHECK-NEXT: 4. 1 4.0 0.0 0.0 addw a0, a0, a0
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 addiw a0, a0, 1
+# CHECK-NEXT: 6. 1 5.0 0.0 0.0 sub a0, a0, a0
+# CHECK-NEXT: 7. 1 6.0 0.0 0.0 subw a0, a0, a0
+# CHECK-NEXT: 8. 1 7.0 0.0 0.0 and a0, a0, a0
+# CHECK-NEXT: 9. 1 8.0 0.0 0.0 andi a0, a0, 1
+# CHECK-NEXT: 10. 1 9.0 0.0 0.0 or a0, a0, a0
+# CHECK-NEXT: 11. 1 10.0 0.0 0.0 ori a0, a0, 1
+# CHECK-NEXT: 12. 1 10.0 0.0 0.0 xor a0, a0, a0
+# CHECK-NEXT: 13. 1 11.0 0.0 0.0 xori a0, a0, 1
+# CHECK-NEXT: 14. 1 12.0 0.0 0.0 sll a0, a0, a0
+# CHECK-NEXT: 15. 1 13.0 0.0 0.0 slli a0, a0, 1
+# CHECK-NEXT: 16. 1 14.0 0.0 0.0 sllw a0, a0, a0
+# CHECK-NEXT: 17. 1 15.0 0.0 0.0 slliw a0, a0, 1
+# CHECK-NEXT: 18. 1 15.0 0.0 0.0 srl a0, a0, a0
+# CHECK-NEXT: 19. 1 16.0 0.0 0.0 srli a0, a0, 1
+# CHECK-NEXT: 20. 1 17.0 0.0 0.0 srlw a0, a0, a0
+# CHECK-NEXT: 21. 1 18.0 0.0 0.0 srliw a0, a0, 1
+# CHECK-NEXT: 22. 1 19.0 0.0 0.0 sra a0, a0, a0
+# CHECK-NEXT: 23. 1 20.0 0.0 0.0 srai a0, a0, 1
+# CHECK-NEXT: 24. 1 20.0 0.0 0.0 sraw a0, a0, a0
+# CHECK-NEXT: 25. 1 21.0 0.0 0.0 sraiw a0, a0, 1
+# CHECK-NEXT: 26. 1 22.0 0.0 0.0 slt a0, a0, a0
+# CHECK-NEXT: 27. 1 23.0 0.0 0.0 slti a0, a0, 1
+# CHECK-NEXT: 28. 1 24.0 0.0 0.0 sltu a0, a0, a0
+# CHECK-NEXT: 29. 1 25.0 0.0 0.0 seqz a0, a0
+# CHECK-NEXT: 30. 1 25.0 0.0 0.0 mul a0, a0, a0
+# CHECK-NEXT: 31. 1 28.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 32. 1 29.0 0.0 0.0 mulw a0, a0, a0
+# CHECK-NEXT: 33. 1 32.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 34. 1 33.0 0.0 0.0 beq a0, a0, .Ltmp0
+# CHECK-NEXT: 35. 1 33.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 36. 1 33.0 0.0 0.0 bne a0, a0, .Ltmp1
+# CHECK-NEXT: 37. 1 33.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 38. 1 34.0 0.0 0.0 blt a0, a0, .Ltmp2
+# CHECK-NEXT: 39. 1 34.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 40. 1 35.0 0.0 0.0 bltu a0, a0, .Ltmp3
+# CHECK-NEXT: 41. 1 35.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 42. 1 35.0 0.0 0.0 bge a0, a0, .Ltmp4
+# CHECK-NEXT: 43. 1 35.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 44. 1 36.0 0.0 0.0 bgeu a0, a0, .Ltmp5
+# CHECK-NEXT: 45. 1 36.0 0.0 0.0 add.uw a0, a0, a0
+# CHECK-NEXT: 46. 1 37.0 0.0 0.0 slli.uw a0, a0, 1
+# CHECK-NEXT: 47. 1 38.0 0.0 0.0 sh1add.uw a0, a0, a0
+# CHECK-NEXT: 48. 1 38.0 0.0 0.0 sh2add.uw a0, a0, a0
+# CHECK-NEXT: 49. 1 39.0 0.0 0.0 sh3add.uw a0, a0, a0
+# CHECK-NEXT: 50. 1 40.0 0.0 0.0 sh1add a0, a0, a0
+# CHECK-NEXT: 51. 1 41.0 0.0 0.0 sh2add a0, a0, a0
+# CHECK-NEXT: 52. 1 42.0 0.0 0.0 sh3add a0, a0, a0
+# CHECK-NEXT: 53. 1 43.0 0.0 0.0 andn a0, a0, a0
+# CHECK-NEXT: 54. 1 43.0 0.0 0.0 orn a0, a0, a0
+# CHECK-NEXT: 55. 1 44.0 0.0 0.0 xnor a0, a0, a0
+# CHECK-NEXT: 56. 1 45.0 0.0 0.0 sext.b a0, a0
+# CHECK-NEXT: 57. 1 46.0 0.0 0.0 sext.h a0, a0
+# CHECK-NEXT: 58. 1 47.0 0.0 0.0 zext.h a0, a0
+# CHECK-NEXT: 59. 1 48.0 0.0 0.0 min a0, a0, a0
+# CHECK-NEXT: 60. 1 48.0 0.0 0.0 minu a0, a0, a0
+# CHECK-NEXT: 61. 1 49.0 0.0 0.0 max a0, a0, a0
+# CHECK-NEXT: 62. 1 50.0 0.0 0.0 maxu a0, a0, a0
+# CHECK-NEXT: 63. 1 51.0 0.0 0.0 rol a0, a0, a0
+# CHECK-NEXT: 64. 1 52.0 0.0 0.0 ror a0, a0, a0
+# CHECK-NEXT: 65. 1 53.0 0.0 0.0 rori a0, a0, 1
+# CHECK-NEXT: 66. 1 53.0 0.0 0.0 clz a0, a0
+# CHECK-NEXT: 67. 1 56.0 0.0 0.0 clzw a0, a0
+# CHECK-NEXT: 68. 1 59.0 0.0 0.0 ctz a0, a0
+# CHECK-NEXT: 69. 1 62.0 0.0 0.0 ctzw a0, a0
+# CHECK-NEXT: 70. 1 65.0 0.0 0.0 cpop a0, a0
+# CHECK-NEXT: 71. 1 68.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 72. 1 68.0 0.0 0.0 cpopw a0, a0
+# CHECK-NEXT: 73. 1 71.0 0.0 0.0 add a0, a0, a0
+# CHECK-NEXT: 74. 1 72.0 0.0 0.0 rev8 a0, a0
+# CHECK-NEXT: 75. 1 73.0 0.0 0.0 orc.b a0, a0
+# CHECK-NEXT: 76. 1 74.0 0.0 0.0 lb a0, 0(a0)
+# CHECK-NEXT: 77. 1 78.0 0.0 1.0 add a0, a0, a0
+# CHECK-NEXT: 78. 1 78.0 0.0 0.0 lh a0, 0(a0)
+# CHECK-NEXT: 79. 1 82.0 0.0 1.0 and a0, a0, a0
+# CHECK-NEXT: 80. 1 83.0 0.0 0.0 lw a0, 0(a0)
+# CHECK-NEXT: 81. 1 87.0 0.0 1.0 or a0, a0, a0
+# CHECK-NEXT: 82. 1 88.0 0.0 0.0 ld a0, 0(a0)
+# CHECK-NEXT: 83. 1 92.0 0.0 1.0 xor a0, a0, a0
+# CHECK-NEXT: 84. 1 92.0 0.0 0.0 lbu a0, 0(a0)
+# CHECK-NEXT: 85. 1 96.0 0.0 1.0 addi a0, a0, 1
+# CHECK-NEXT: 86. 1 97.0 0.0 0.0 lhu a0, 0(a0)
+# CHECK-NEXT: 87. 1 101.0 0.0 1.0 sub a0, a0, a0
+# CHECK-NEXT: 88. 1 102.0 0.0 0.0 lwu a0, 0(a0)
+# CHECK-NEXT: 89. 1 106.0 0.0 1.0 addw a0, a0, a0
+# CHECK-NEXT: 90. 1 106.0 0.0 0.0 jr a0
+# CHECK-NEXT: 1 41.8 0.0 0.1 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s
new file mode 100644
index 00000000000000..def4ce1b284f39
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s
@@ -0,0 +1,10 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s 2>&1 | FileCheck %s
+
+# Kunminghu does not support the Zvfhmin and Zvfh extensions,
+# then floating-point SEW can only be 64 and 32, not 16 and 8.
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vv v4, v8, v12
+
+# CHECK: error: found an unsupported instruction in the input assembly sequence.
+# CHECK-NEXT: note: instruction: vfdiv.vv v4, v8, v12
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/vector-integer-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/vector-integer-arithmetic.s
new file mode 100644
index 00000000000000..fcb194ca928683
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan/vector-integer-arithmetic.s
@@ -0,0 +1,2271 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e16, mf4, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e16, m1, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e16, m2, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e32, mf2, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e32, m1, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e32, m8, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vadd.vv v4, v8, v12
+
+# Vector Widening Integer Add/Subtract
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwaddu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwaddu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwsubu.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwsubu.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwadd.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwadd.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwsub.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwsub.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwaddu.wv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwaddu.wx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwsubu.wv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwsubu.wx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwadd.wv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwadd.wx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwsub.wv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwsub.wx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwaddu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwaddu.vx v4, v8, x10
+
+# Vector Integer Extension
+# no e8
+vsetvli zero, zero, e16, mf4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+
+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmadc.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmadc.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmadc.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsbc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vsbc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmsbc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmsbc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsbc.vv v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsbc.vx v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmadc.vv v4, v8, v12
+
+# Vector Bitwise Logical Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vor.vv v4, v8, v12
+
+# Vector Single-Width Shift Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vsrl.vv v4, v8, v12
+
+# Vector Narrowing Integer Right Shift Instructions
+# no e8
+vsetvli zero, zero, e8, mf8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vnsra.wv v4, v8, v12
+
+# Vector Integer Compare Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmseq.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmseq.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmsne.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmsne.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmsne.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmsltu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmsltu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmslt.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmslt.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmsleu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmsleu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmsleu.vi v4, v8, 0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsle.vv v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsle.vx v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vmsle.vi v4, v8, 0
+vsetvli zero, zero, e32, m4, tu, mu
+vmsgtu.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmsgtu.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmsgt.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vmsgt.vi v4, v8, 0
+vsetvli zero, zero, e64, m4, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmseq.vx v4, v8, x10
+
+# Pseudo instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmslt.vi v4, v8, 1
+vsetvli zero, zero, e8, mf4, tu, mu
+vmsltu.vi v4, v8, 1
+vsetvli zero, zero, e8, mf2, tu, mu
+vmsltu.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmsgeu.vi v4, v8, 1
+vsetvli zero, zero, e8, m2, tu, mu
+vmsge.vi v4, v8, 1
+vsetvli zero, zero, e8, m4, tu, mu
+vmsgeu.vi v4, v8, 0
+vsetvli zero, zero, e16, mf4, tu, mu
+vmsge.vi v4, v8, 0
+vsetvli zero, zero, e16, mf2, tu, mu
+vmsge.vx v4, v8, x10
+vsetvli zero, zero, e16, m1, tu, mu
+vmsgeu.vx v4, v8, x11
+
+# Vector Integer Min/Max Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmaxu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmulhu.vx v4, v8, x10
+
+# Vector Integer Divide Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vremu.vx v4, v8, x10
+
+# Vector Widening Integer Multiply Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwmulsu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply-Add Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vmadd.vx v4, x10, v8
+
+# Vector Widening Integer Multiply-Add Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vwmacc.vx v4, x10, v8
+
+# Vector Integer Merge Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m1, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e32, m2, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+
+# Vector Integer Move Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vmv.v.v v4, v12
+
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 727
+# CHECK-NEXT: Total Cycles: 610
+# CHECK-NEXT: Total uOps: 727
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.19
+# CHECK-NEXT: IPC: 1.19
+# CHECK-NEXT: Block RThroughput: 342.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vwaddu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vwaddu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vwsubu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vwsubu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vwadd.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vwadd.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 0.50 vwsub.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vwsub.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vwaddu.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vwaddu.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vwsubu.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vwsubu.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 0.50 vwadd.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vwadd.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vwsub.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vwsub.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vwaddu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 0.50 vwaddu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 8 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 16 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 2 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 2 0.50 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 2 0.50 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 0.50 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 4 0.50 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 8 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 8 0.50 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 8 0.50 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 16 0.50 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 16 0.50 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 16 0.50 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmadc.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmadc.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmadc.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vmsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmsbc.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsbc.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmadc.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vor.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vor.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vxor.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vxor.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vxor.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vor.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vor.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vxor.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vxor.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vxor.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vsrl.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vsrl.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vsra.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsra.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsra.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsrl.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vsrl.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vsra.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vsra.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vsra.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 0.50 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 0.50 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 0.50 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 0.50 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmseq.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmseq.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmseq.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmsne.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmsne.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmsne.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmsltu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsltu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmslt.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmslt.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vmsleu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmsleu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmsleu.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmsle.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsle.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmsle.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmsgtu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmsgtu.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsgt.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmsgt.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vmseq.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmseq.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsle.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsleu.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmsne.vv v4, v8, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsgtu.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmsgt.vi v4, v8, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vmseq.vv v4, v8, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsgt.vi v4, v8, -1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmslt.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 vmnot.m v4, v4
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmsltu.vx v4, v8, a1
+# CHECK-NEXT: 1 2 0.50 vmnot.m v4, v4
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmax.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmax.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmax.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmax.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 0.50 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 24 1.00 vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 24 1.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 25 1.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 25 1.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 1.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 25 1.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 1.00 vrem.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vrem.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 1.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 14 1.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 29 1.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 56 1.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 1.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 11 1.00 vrem.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 23 1.00 vrem.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 1.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 89 1.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 19 1.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 39 1.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 1.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 153 1.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 1.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 12 1.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 24 1.00 vnmsub.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vnmsub.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 24 1.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vnmsub.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vnmsub.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 25 1.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 25 1.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 1.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 1.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 1.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 vmv.v.v v4, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 0.50 vmv.v.x v4, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 0.50 vmv.v.i v4, 0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 0.50 vmv.v.v v4, v12
+
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipVFEX0
+# CHECK-NEXT: [1] - XSPipVFEX1
+# CHECK-NEXT: [2] - XSPipVFEX2
+# CHECK-NEXT: [3] - XSPipVFEX3
+# CHECK-NEXT: [4] - XSPipVLDU
+# CHECK-NEXT: [5] - XSPipVSTU
+# CHECK-NEXT: [6] - XSPipeALU0
+# CHECK-NEXT: [7] - XSPipeALU1
+# CHECK-NEXT: [8] - XSPipeALU2
+# CHECK-NEXT: [9] - XSPipeALU3
+# CHECK-NEXT: [10] - XSPipeBJU0
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+# CHECK-NEXT: [12] - XSPipeBJU2
+# CHECK-NEXT: [13] - XSPipeDIV
+# CHECK-NEXT: [14] - XSPipeLDU0
+# CHECK-NEXT: [15] - XSPipeLDU1
+# CHECK-NEXT: [16] - XSPipeLDU2
+# CHECK-NEXT: [17] - XSPipeSTU0
+# CHECK-NEXT: [18] - XSPipeSTU1
+
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
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+# CHECK: Resource pressure by instruction:
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