[llvm] [AMDGPU] GISelShouldIgnore .td uses (PR #90005)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 16:48:43 PDT 2024
https://github.com/jofrn created https://github.com/llvm/llvm-project/pull/90005
[#88382](https://github.com/llvm/llvm-project/pull/88382) implements the new bit for `class Pattern` in `TargetSelectionDAG.td`.
This applies it to all affected Pattern records with a `warning: Skipped pattern:` from `-warn-on-skipped-patterns`.
>From f4e7c49aebeed2d253049d86943c36681c17f84c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 11 Apr 2024 01:15:36 -0400
Subject: [PATCH 01/13] [TableGen] New tblgen Instruction bit to disable
DAGISel pattern imports
Added a new DAGISelShouldIgnore property to class Instruction in Target.td, similar to FastISelShouldIgnore. This allows one to avoid a record's DAGISel .td implementation and .inc generation.
---
llvm/include/llvm/Target/Target.td | 4 ++++
llvm/utils/TableGen/Common/CodeGenInstruction.cpp | 1 +
llvm/utils/TableGen/Common/CodeGenInstruction.h | 1 +
llvm/utils/TableGen/DAGISelEmitter.cpp | 15 ++++++++++++++-
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 1f7dc6922f13e4..61dc04595b62b9 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,6 +777,10 @@ class Instruction : InstructionEncoding {
/// SelectionDAG can.
bit FastISelShouldIgnore = false;
+ /// Should DAGISel ignore this instruction. In cases where lowering may
+ /// be done elsewhere or is unneeded, DAGISel may skip over them.
+ bit DAGISelShouldIgnore = false;
+
/// HasPositionOrder: Indicate tablegen to sort the instructions by record
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index 18a4e7b0f18b23..a76efb76bfc319 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,6 +465,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
+ DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
isAuthenticated = R->getValueAsBit("isAuthenticated");
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index b658259b4892ee..c36bfba245f66b 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,6 +282,7 @@ class CodeGenInstruction {
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
+ bool DAGISelShouldIgnore : 1;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b43a8e659dd9c5..4fbeafdc2355fb 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,8 +165,21 @@ void DAGISelEmitter::run(raw_ostream &OS) {
// Add all the patterns to a temporary list so we can sort them.
Records.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
- for (const PatternToMatch &PTM : CGP.ptms())
+ for (const PatternToMatch &PTM : CGP.ptms()) {
+
+ // Disable import of patterns marked as ignore.
+ const TreePatternNode &Dst = PTM.getDstPattern();
+ if (!Dst.isLeaf()) {
+ const Record *Op = Dst.getOperator();
+ const bool shouldIgnore =
+ Op->isSubClassOf("Instruction") &&
+ CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
+ if (shouldIgnore)
+ continue;
+ }
+
Patterns.push_back(&PTM);
+ }
// We want to process the matches in order of minimal cost. Sort the patterns
// so the least cost one is at the start.
>From ad38450e674b228eeb5735aa41c7c5c9331e559c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 12 Apr 2024 12:14:38 -0400
Subject: [PATCH 02/13] [TableGen] Add test for DAGISelShouldIgnore
This test ensures no .inc code is generated in the MatcherTable for the corresponding marked .td record.
---
.../TableGen/DAGISelEmitter-shouldignore.td | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 llvm/test/TableGen/DAGISelEmitter-shouldignore.td
diff --git a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
new file mode 100644
index 00000000000000..61dac212a716e0
--- /dev/null
+++ b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s -DIGNORE | FileCheck %s
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s --match-prefix=CHECK_LOOK | FileCheck --check-prefix=CHECK_LOOK %s
+
+include "llvm/Target/Target.td"
+def ISA : InstrInfo;
+def Tgt : Target { let InstructionSet = ISA; }
+def R0 : Register<"r0"> { let Namespace = "Tgt"; }
+def RC : RegisterClass<"Tgt", [i32], 32, (add R0)>;
+def Op : RegisterOperand<RC>;
+
+class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
+ let Namespace = "Tgt";
+ let OutOperandList = OOps;
+ let InOperandList = IOps;
+ let Pattern = Pat;
+}
+
+#ifdef IGNORE
+let DAGISelShouldIgnore = 1 in
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt), []>;
+// CHECK: static const unsigned char MatcherTable[] = {
+// CHECK-NEXT: 0
+// CHECK-NEXT: }; // Total Array size is 1 bytes
+#else
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt),
+ [(set Op:$rd, (add Op:$rs, Op:$rt))]>;
+// CHECK_LOOK:static const unsigned char MatcherTable[] = {
+// CHECK_LOOK-NEXT:/* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+// CHECK_LOOK-NEXT:/* 3*/ OPC_RecordChild0, // #0 = $rs
+// CHECK_LOOK-NEXT:/* 4*/ OPC_RecordChild1, // #1 = $rt
+// CHECK_LOOK-NEXT:/* 5*/ OPC_MorphNodeTo1None, TARGET_VAL(Tgt::ADD),
+// CHECK_LOOK-NEXT: MVT::i32, 2/*#Ops*/, 0, 1,
+// CHECK_LOOK-NEXT:// Src: (add:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt) - Complexity = {{[0-9]+}}
+// CHECK_LOOK-NEXT:// Dst: (ADD:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt)
+// CHECK_LOOK-NEXT: 0
+// CHECK_LOOK-NEXT:}; // Total Array size is 13 bytes
+#endif
>From c206eb60ee2c2881ffb895ea607f4a1918df11b3 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 18 Apr 2024 17:23:44 -0400
Subject: [PATCH 03/13] [TableGen] Added tblgen ISelShouldIgnore bit to class
Pattern to disable pattern imports in GISel
Via `let ISelShouldIgnore = 1`, a Pattern record can be disabled to skip pattern warnings in GlobalISel.
---
llvm/include/llvm/Target/TargetSelectionDAG.td | 1 +
.../TableGen/GlobalISelEmitterSkippedPatterns.td | 6 ++++++
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 10 ++++++----
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 13 ++++++++-----
llvm/utils/TableGen/GlobalISelEmitter.cpp | 15 ++++++++++-----
5 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index ea3520835fa07d..eeef17674eac55 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -1979,6 +1979,7 @@ class Pattern<dag patternToMatch, list<dag> resultInstrs> {
list<dag> ResultInstrs = resultInstrs;
list<Predicate> Predicates = []; // See class Instruction in Target.td.
int AddedComplexity = 0; // See class Instruction in Target.td.
+ bit ISelShouldIgnore = 0;
}
// Pat - A simple (but common) form of a pattern, which produces a simple result
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index 7c9df02ebd87c6..5554b6f9000535 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,4 +1,6 @@
// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=CHECK0 %s
+
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -23,6 +25,10 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
//===- Bail out when we define a variable twice wrt complex suboperands. -===//
+#ifdef IGNORE
+let ISelShouldIgnore = 1 in
+#endif
+// CHECK0-NOT: warning: Skipped pattern: Error: {{.*}}
// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
def : Pat<(add (complex_rr GPR32:$x, GPR32:$y),
(complex_rr GPR32:$x, GPR32:$z)),
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 7a5d2be3ae95b2..7bccdbe8b5d724 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4246,7 +4246,7 @@ static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
void CodeGenDAGPatterns::ParseOnePattern(
Record *TheDef, TreePattern &Pattern, TreePattern &Result,
- const std::vector<Record *> &InstImpResults) {
+ const std::vector<Record *> &InstImpResults, bool ShouldIgnore) {
// Inline pattern fragments and expand multiple alternatives.
Pattern.InlinePatternFragments();
@@ -4332,7 +4332,7 @@ void CodeGenDAGPatterns::ParseOnePattern(
AddPatternToMatch(&Pattern,
PatternToMatch(TheDef, Preds, T, Temp.getOnlyTree(),
InstImpResults, Complexity,
- TheDef->getID()));
+ TheDef->getID(), ShouldIgnore));
}
} else {
// Show a message about a dropped pattern with some info to make it
@@ -4378,7 +4378,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
- ParseOnePattern(CurPattern, Pattern, Result, InstImpResults);
+ ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
+ CurPattern->getValueAsBit("ISelShouldIgnore"));
}
}
@@ -4410,7 +4411,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
std::move(NewSrc), std::move(NewDst),
P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), Check);
+ Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4781,6 +4782,7 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
+ PatternsToMatch[i].getISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 7fcd39a9e940cc..6a85a579658892 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,16 +1057,17 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ bool ISelShouldIgnore; // Should ISel ignore this pattern.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, bool ignore, const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
- HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
+ HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity), ISelShouldIgnore(ignore),
ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
@@ -1078,6 +1079,7 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
+ bool getISelShouldIgnore() const { return ISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
@@ -1240,7 +1242,8 @@ class CodeGenDAGPatterns {
void ParseOnePattern(Record *TheDef, TreePattern &Pattern,
TreePattern &Result,
- const std::vector<Record *> &InstImpResults);
+ const std::vector<Record *> &InstImpResults,
+ bool ShouldIgnore = false);
void AddPatternToMatch(TreePattern *Pattern, PatternToMatch &&PTM);
void FindPatternInputsAndOutputs(
TreePattern &I, TreePatternNodePtr Pat,
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 25e302ce1ca46f..f379476eeeb59f 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -428,7 +428,7 @@ class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
/// Analyze pattern \p P, returning a matcher for it if possible.
/// Otherwise, return an Error explaining why we don't support it.
- Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
+ std::optional<Expected<RuleMatcher>> runOnPattern(const PatternToMatch &P);
void declareSubtargetFeature(Record *Predicate);
@@ -1901,7 +1901,11 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+std::optional<Expected<RuleMatcher>> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+ if (P.getISelShouldIgnore()) {
+ return {};
+ }
+
// Keep track of the matchers and actions to emit.
int Score = P.getPatternComplexity(CGP);
RuleMatcher M(P.getSrcRecord()->getLoc());
@@ -2412,10 +2416,11 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
++NumPatternTotal;
auto MatcherOrErr = runOnPattern(Pat);
+ if (!MatcherOrErr) continue; // skip without warning
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
- if (auto Err = MatcherOrErr.takeError()) {
+ if (auto Err = MatcherOrErr->takeError()) {
if (WarnOnSkippedPatterns) {
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Skipped pattern: " + toString(std::move(Err)));
@@ -2427,13 +2432,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
}
if (RuleCoverage) {
- if (RuleCoverage->isCovered(MatcherOrErr->getRuleID()))
+ if (RuleCoverage->isCovered((*MatcherOrErr)->getRuleID()))
++NumPatternsTested;
else
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Pattern is not covered by a test");
}
- Rules.push_back(std::move(MatcherOrErr.get()));
+ Rules.push_back(std::move(MatcherOrErr->get()));
postProcessRule(Rules.back());
}
>From d49299eaf49dc9881ab471c3165f41a9c026d792 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 18 Apr 2024 19:15:54 -0400
Subject: [PATCH 04/13] [TableGen] clang-format for ShouldIgnore
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 8 ++++----
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 7 ++++---
llvm/utils/TableGen/DAGISelEmitter.cpp | 4 ++--
llvm/utils/TableGen/GlobalISelEmitter.cpp | 6 ++++--
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 7bccdbe8b5d724..a75e2bc4d116d2 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4408,10 +4408,10 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
return;
}
- PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
- std::move(NewSrc), std::move(NewDst),
- P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
+ PatternsToMatch.emplace_back(
+ P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
+ std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
+ Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 6a85a579658892..723e042b3c199f 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1064,11 +1064,12 @@ class PatternToMatch {
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, bool ignore, const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, bool ignore,
+ const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
- HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity), ISelShouldIgnore(ignore),
- ID(uid) {}
+ HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
+ ISelShouldIgnore(ignore), ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 4fbeafdc2355fb..b1a3acf4b2f451 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -171,10 +171,10 @@ void DAGISelEmitter::run(raw_ostream &OS) {
const TreePatternNode &Dst = PTM.getDstPattern();
if (!Dst.isLeaf()) {
const Record *Op = Dst.getOperator();
- const bool shouldIgnore =
+ const bool ShouldIgnore =
Op->isSubClassOf("Instruction") &&
CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
- if (shouldIgnore)
+ if (ShouldIgnore)
continue;
}
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index f379476eeeb59f..aec16ecdcb6770 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -1901,7 +1901,8 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-std::optional<Expected<RuleMatcher>> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+std::optional<Expected<RuleMatcher>>
+GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
if (P.getISelShouldIgnore()) {
return {};
}
@@ -2416,7 +2417,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
++NumPatternTotal;
auto MatcherOrErr = runOnPattern(Pat);
- if (!MatcherOrErr) continue; // skip without warning
+ if (!MatcherOrErr)
+ continue; // skip without warning
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
>From c10ab41689367050919dedc72cf920fd037bade8 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 09:24:01 -0400
Subject: [PATCH 05/13] [TableGen] style and names for GISelShouldIgnore
---
.../include/llvm/Target/TargetSelectionDAG.td | 2 +-
.../GlobalISelEmitterSkippedPatterns.td | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.cpp | 6 +++---
.../TableGen/Common/CodeGenDAGPatterns.h | 10 +++++-----
llvm/utils/TableGen/GlobalISelEmitter.cpp | 19 +++++++------------
5 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index eeef17674eac55..1684b424e3b442 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -1979,7 +1979,7 @@ class Pattern<dag patternToMatch, list<dag> resultInstrs> {
list<dag> ResultInstrs = resultInstrs;
list<Predicate> Predicates = []; // See class Instruction in Target.td.
int AddedComplexity = 0; // See class Instruction in Target.td.
- bit ISelShouldIgnore = 0;
+ bit GISelShouldIgnore = 0;
}
// Pat - A simple (but common) form of a pattern, which produces a simple result
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index 5554b6f9000535..d85e43c6bfb450 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -26,7 +26,7 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
//===- Bail out when we define a variable twice wrt complex suboperands. -===//
#ifdef IGNORE
-let ISelShouldIgnore = 1 in
+let GISelShouldIgnore = 1 in
#endif
// CHECK0-NOT: warning: Skipped pattern: Error: {{.*}}
// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index a75e2bc4d116d2..88d353e89a4614 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4379,7 +4379,7 @@ void CodeGenDAGPatterns::ParsePatterns() {
InstResults, InstImpResults);
ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
- CurPattern->getValueAsBit("ISelShouldIgnore"));
+ CurPattern->getValueAsBit("GISelShouldIgnore"));
}
}
@@ -4411,7 +4411,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
PatternsToMatch.emplace_back(
P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
+ Record::getNewUID(Records), P.getGISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4782,7 +4782,7 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
- PatternsToMatch[i].getISelShouldIgnore(),
+ PatternsToMatch[i].getGISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 723e042b3c199f..7f94db0b7d5d76 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,9 +1057,9 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- bool ISelShouldIgnore; // Should ISel ignore this pattern.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ bool GISelShouldIgnore; // Should GlobalISel ignore importing this pattern.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
@@ -1069,7 +1069,7 @@ class PatternToMatch {
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
- ISelShouldIgnore(ignore), ID(uid) {}
+ GISelShouldIgnore(ignore), ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
@@ -1080,7 +1080,7 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
- bool getISelShouldIgnore() const { return ISelShouldIgnore; }
+ bool getGISelShouldIgnore() const { return GISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index aec16ecdcb6770..78abf80e7aecb3 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -428,7 +428,7 @@ class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
/// Analyze pattern \p P, returning a matcher for it if possible.
/// Otherwise, return an Error explaining why we don't support it.
- std::optional<Expected<RuleMatcher>> runOnPattern(const PatternToMatch &P);
+ Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
void declareSubtargetFeature(Record *Predicate);
@@ -1901,12 +1901,7 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-std::optional<Expected<RuleMatcher>>
-GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
- if (P.getISelShouldIgnore()) {
- return {};
- }
-
+Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
// Keep track of the matchers and actions to emit.
int Score = P.getPatternComplexity(CGP);
RuleMatcher M(P.getSrcRecord()->getLoc());
@@ -2416,13 +2411,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
for (const PatternToMatch &Pat : CGP.ptms()) {
++NumPatternTotal;
- auto MatcherOrErr = runOnPattern(Pat);
- if (!MatcherOrErr)
+ if (Pat.getGISelShouldIgnore())
continue; // skip without warning
+ auto MatcherOrErr = runOnPattern(Pat);
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
- if (auto Err = MatcherOrErr->takeError()) {
+ if (auto Err = MatcherOrErr.takeError()) {
if (WarnOnSkippedPatterns) {
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Skipped pattern: " + toString(std::move(Err)));
@@ -2434,13 +2429,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
}
if (RuleCoverage) {
- if (RuleCoverage->isCovered((*MatcherOrErr)->getRuleID()))
+ if (RuleCoverage->isCovered(MatcherOrErr->getRuleID()))
++NumPatternsTested;
else
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Pattern is not covered by a test");
}
- Rules.push_back(std::move(MatcherOrErr->get()));
+ Rules.push_back(std::move(MatcherOrErr.get()));
postProcessRule(Rules.back());
}
>From e9287d30404a916ced37b64ee1f1f674f15aa967 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 10:01:41 -0400
Subject: [PATCH 06/13] [TableGen] Add .inc test for GISelShouldIgnore
This test ensures the MatchTable has no patterns marked with GISelShouldIgnore.
---
llvm/test/TableGen/GlobalISelEmitterVariadic.td | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
index ba6a93bd4837f2..05da0cbc36f9cd 100644
--- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
@@ -1,4 +1,5 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - -DIGNORE | FileCheck %s --check-prefix=CHECK0
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -17,11 +18,20 @@ def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def : Pat<(build_vector GPR32:$src1),
(ONE GPR32:$src1)> {
let AddedComplexity = 1000;
+#ifdef IGNORE
+ let GISelShouldIgnore = 1;
+#endif
}
+#ifdef IGNORE
+let GISelShouldIgnore = 1 in
+#endif
def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
(TWO GPR32:$src1, GPR32:$src2)>;
+// CHECK0: constexpr static uint8_t MatchTable0[] = {
+// CHECK0-NEXT: GIM_Reject,
+// CHECK0-NEXT:}; // Size: 1 bytes
// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4([[NEXT_OPCODE_LABEL:[0-9]+]]),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 //
>From 5fbc5eeb72f5d4bf375cffcc204c28ea5d7ac5ca Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 10:12:30 -0400
Subject: [PATCH 07/13] [TableGen] Remove ShouldIgnore bit on Instruction ; not
needed for dagisel
---
llvm/include/llvm/Target/Target.td | 4 --
.../TableGen/DAGISelEmitter-shouldignore.td | 37 -------------------
.../TableGen/Common/CodeGenInstruction.cpp | 1 -
.../TableGen/Common/CodeGenInstruction.h | 1 -
llvm/utils/TableGen/DAGISelEmitter.cpp | 15 +-------
5 files changed, 1 insertion(+), 57 deletions(-)
delete mode 100644 llvm/test/TableGen/DAGISelEmitter-shouldignore.td
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 61dc04595b62b9..1f7dc6922f13e4 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,10 +777,6 @@ class Instruction : InstructionEncoding {
/// SelectionDAG can.
bit FastISelShouldIgnore = false;
- /// Should DAGISel ignore this instruction. In cases where lowering may
- /// be done elsewhere or is unneeded, DAGISel may skip over them.
- bit DAGISelShouldIgnore = false;
-
/// HasPositionOrder: Indicate tablegen to sort the instructions by record
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
diff --git a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
deleted file mode 100644
index 61dac212a716e0..00000000000000
--- a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
+++ /dev/null
@@ -1,37 +0,0 @@
-// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s -DIGNORE | FileCheck %s
-// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s --match-prefix=CHECK_LOOK | FileCheck --check-prefix=CHECK_LOOK %s
-
-include "llvm/Target/Target.td"
-def ISA : InstrInfo;
-def Tgt : Target { let InstructionSet = ISA; }
-def R0 : Register<"r0"> { let Namespace = "Tgt"; }
-def RC : RegisterClass<"Tgt", [i32], 32, (add R0)>;
-def Op : RegisterOperand<RC>;
-
-class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
- let Namespace = "Tgt";
- let OutOperandList = OOps;
- let InOperandList = IOps;
- let Pattern = Pat;
-}
-
-#ifdef IGNORE
-let DAGISelShouldIgnore = 1 in
-def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt), []>;
-// CHECK: static const unsigned char MatcherTable[] = {
-// CHECK-NEXT: 0
-// CHECK-NEXT: }; // Total Array size is 1 bytes
-#else
-def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt),
- [(set Op:$rd, (add Op:$rs, Op:$rt))]>;
-// CHECK_LOOK:static const unsigned char MatcherTable[] = {
-// CHECK_LOOK-NEXT:/* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
-// CHECK_LOOK-NEXT:/* 3*/ OPC_RecordChild0, // #0 = $rs
-// CHECK_LOOK-NEXT:/* 4*/ OPC_RecordChild1, // #1 = $rt
-// CHECK_LOOK-NEXT:/* 5*/ OPC_MorphNodeTo1None, TARGET_VAL(Tgt::ADD),
-// CHECK_LOOK-NEXT: MVT::i32, 2/*#Ops*/, 0, 1,
-// CHECK_LOOK-NEXT:// Src: (add:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt) - Complexity = {{[0-9]+}}
-// CHECK_LOOK-NEXT:// Dst: (ADD:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt)
-// CHECK_LOOK-NEXT: 0
-// CHECK_LOOK-NEXT:}; // Total Array size is 13 bytes
-#endif
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index a76efb76bfc319..18a4e7b0f18b23 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,7 +465,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
- DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
isAuthenticated = R->getValueAsBit("isAuthenticated");
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index c36bfba245f66b..b658259b4892ee 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,7 +282,6 @@ class CodeGenInstruction {
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
- bool DAGISelShouldIgnore : 1;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b1a3acf4b2f451..b43a8e659dd9c5 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,21 +165,8 @@ void DAGISelEmitter::run(raw_ostream &OS) {
// Add all the patterns to a temporary list so we can sort them.
Records.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
- for (const PatternToMatch &PTM : CGP.ptms()) {
-
- // Disable import of patterns marked as ignore.
- const TreePatternNode &Dst = PTM.getDstPattern();
- if (!Dst.isLeaf()) {
- const Record *Op = Dst.getOperator();
- const bool ShouldIgnore =
- Op->isSubClassOf("Instruction") &&
- CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
- if (ShouldIgnore)
- continue;
- }
-
+ for (const PatternToMatch &PTM : CGP.ptms())
Patterns.push_back(&PTM);
- }
// We want to process the matches in order of minimal cost. Sort the patterns
// so the least cost one is at the start.
>From af2c62e738462b3461b3c6d5657d4c2cc59e0923 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 11:21:38 -0400
Subject: [PATCH 08/13] [TableGen] Move pattern import disabling earlier
---
.../TableGen/Common/CodeGenDAGPatterns.cpp | 17 ++++++++---------
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 14 +++++---------
llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 --
3 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 88d353e89a4614..516c33260c9978 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4246,7 +4246,7 @@ static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
void CodeGenDAGPatterns::ParseOnePattern(
Record *TheDef, TreePattern &Pattern, TreePattern &Result,
- const std::vector<Record *> &InstImpResults, bool ShouldIgnore) {
+ const std::vector<Record *> &InstImpResults) {
// Inline pattern fragments and expand multiple alternatives.
Pattern.InlinePatternFragments();
@@ -4332,7 +4332,7 @@ void CodeGenDAGPatterns::ParseOnePattern(
AddPatternToMatch(&Pattern,
PatternToMatch(TheDef, Preds, T, Temp.getOnlyTree(),
InstImpResults, Complexity,
- TheDef->getID(), ShouldIgnore));
+ TheDef->getID()));
}
} else {
// Show a message about a dropped pattern with some info to make it
@@ -4378,8 +4378,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
- ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
- CurPattern->getValueAsBit("GISelShouldIgnore"));
+ if (!CurPattern->getValueAsBit("GISelShouldIgnore"))
+ ParseOnePattern(CurPattern, Pattern, Result, InstImpResults);
}
}
@@ -4408,10 +4408,10 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
return;
}
- PatternsToMatch.emplace_back(
- P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
- std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), P.getGISelShouldIgnore(), Check);
+ PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
+ std::move(NewSrc), std::move(NewDst),
+ P.getDstRegs(), P.getAddedComplexity(),
+ Record::getNewUID(Records), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4782,7 +4782,6 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
- PatternsToMatch[i].getGISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 7f94db0b7d5d76..7fcd39a9e940cc 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,19 +1057,17 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- bool GISelShouldIgnore; // Should GlobalISel ignore importing this pattern.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, bool ignore,
- const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
- GISelShouldIgnore(ignore), ID(uid) {}
+ ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
@@ -1080,7 +1078,6 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
- bool getGISelShouldIgnore() const { return GISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
@@ -1243,8 +1240,7 @@ class CodeGenDAGPatterns {
void ParseOnePattern(Record *TheDef, TreePattern &Pattern,
TreePattern &Result,
- const std::vector<Record *> &InstImpResults,
- bool ShouldIgnore = false);
+ const std::vector<Record *> &InstImpResults);
void AddPatternToMatch(TreePattern *Pattern, PatternToMatch &&PTM);
void FindPatternInputsAndOutputs(
TreePattern &I, TreePatternNodePtr Pat,
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 78abf80e7aecb3..25e302ce1ca46f 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2411,8 +2411,6 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
for (const PatternToMatch &Pat : CGP.ptms()) {
++NumPatternTotal;
- if (Pat.getGISelShouldIgnore())
- continue; // skip without warning
auto MatcherOrErr = runOnPattern(Pat);
// The pattern analysis can fail, indicating an unsupported pattern.
>From 476149d18974a0ebf79c9131ff53b29f2d68aa60 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Mon, 22 Apr 2024 14:02:47 -0400
Subject: [PATCH 09/13] [TableGen] Remove .inc test
The intended usage of ShouldIgnore is to disable warnings. This test
checks the .inc Emitter output of GISel only. So we can remove it here.
---
llvm/test/TableGen/GlobalISelEmitterVariadic.td | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
index 05da0cbc36f9cd..ba6a93bd4837f2 100644
--- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
@@ -1,5 +1,4 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - -DIGNORE | FileCheck %s --check-prefix=CHECK0
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -18,20 +17,11 @@ def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def : Pat<(build_vector GPR32:$src1),
(ONE GPR32:$src1)> {
let AddedComplexity = 1000;
-#ifdef IGNORE
- let GISelShouldIgnore = 1;
-#endif
}
-#ifdef IGNORE
-let GISelShouldIgnore = 1 in
-#endif
def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
(TWO GPR32:$src1, GPR32:$src2)>;
-// CHECK0: constexpr static uint8_t MatchTable0[] = {
-// CHECK0-NEXT: GIM_Reject,
-// CHECK0-NEXT:}; // Size: 1 bytes
// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4([[NEXT_OPCODE_LABEL:[0-9]+]]),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 //
>From c72fc5ff68730a881c1f378452ed152b0d479063 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Wed, 24 Apr 2024 18:43:54 -0400
Subject: [PATCH 10/13] [TableGen] Move check to be within GlobalISelEmitter
only.
Otherwise, the DAG is affected.
---
.../TableGen/Common/CodeGenDAGPatterns.cpp | 17 +++++++++--------
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 14 +++++++++-----
llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 ++
3 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 516c33260c9978..88d353e89a4614 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4246,7 +4246,7 @@ static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
void CodeGenDAGPatterns::ParseOnePattern(
Record *TheDef, TreePattern &Pattern, TreePattern &Result,
- const std::vector<Record *> &InstImpResults) {
+ const std::vector<Record *> &InstImpResults, bool ShouldIgnore) {
// Inline pattern fragments and expand multiple alternatives.
Pattern.InlinePatternFragments();
@@ -4332,7 +4332,7 @@ void CodeGenDAGPatterns::ParseOnePattern(
AddPatternToMatch(&Pattern,
PatternToMatch(TheDef, Preds, T, Temp.getOnlyTree(),
InstImpResults, Complexity,
- TheDef->getID()));
+ TheDef->getID(), ShouldIgnore));
}
} else {
// Show a message about a dropped pattern with some info to make it
@@ -4378,8 +4378,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
- if (!CurPattern->getValueAsBit("GISelShouldIgnore"))
- ParseOnePattern(CurPattern, Pattern, Result, InstImpResults);
+ ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
+ CurPattern->getValueAsBit("GISelShouldIgnore"));
}
}
@@ -4408,10 +4408,10 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
return;
}
- PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
- std::move(NewSrc), std::move(NewDst),
- P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), Check);
+ PatternsToMatch.emplace_back(
+ P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
+ std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
+ Record::getNewUID(Records), P.getGISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4782,6 +4782,7 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
+ PatternsToMatch[i].getGISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 7fcd39a9e940cc..7f94db0b7d5d76 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,17 +1057,19 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ bool GISelShouldIgnore; // Should GlobalISel ignore importing this pattern.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, bool ignore,
+ const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
- ID(uid) {}
+ GISelShouldIgnore(ignore), ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
@@ -1078,6 +1080,7 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
+ bool getGISelShouldIgnore() const { return GISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
@@ -1240,7 +1243,8 @@ class CodeGenDAGPatterns {
void ParseOnePattern(Record *TheDef, TreePattern &Pattern,
TreePattern &Result,
- const std::vector<Record *> &InstImpResults);
+ const std::vector<Record *> &InstImpResults,
+ bool ShouldIgnore = false);
void AddPatternToMatch(TreePattern *Pattern, PatternToMatch &&PTM);
void FindPatternInputsAndOutputs(
TreePattern &I, TreePatternNodePtr Pat,
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 25e302ce1ca46f..78abf80e7aecb3 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2411,6 +2411,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
for (const PatternToMatch &Pat : CGP.ptms()) {
++NumPatternTotal;
+ if (Pat.getGISelShouldIgnore())
+ continue; // skip without warning
auto MatcherOrErr = runOnPattern(Pat);
// The pattern analysis can fail, indicating an unsupported pattern.
>From f1f340f17cc1e982ec89ea2993f0aaafc9851a4e Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Wed, 24 Apr 2024 18:47:14 -0400
Subject: [PATCH 11/13] [TableGen] name change a FileCheck --check-prefix
---
llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index d85e43c6bfb450..fc8abc6fbc547e 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,5 +1,5 @@
// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=CHECK0 %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=IGNORED %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -28,7 +28,7 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
#ifdef IGNORE
let GISelShouldIgnore = 1 in
#endif
-// CHECK0-NOT: warning: Skipped pattern: Error: {{.*}}
+// IGNORED-NOT: warning: Skipped pattern: Error: {{.*}}
// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
def : Pat<(add (complex_rr GPR32:$x, GPR32:$y),
(complex_rr GPR32:$x, GPR32:$z)),
>From 7d110220cd325f4be11304ac7256b0d368eab089 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Wed, 24 Apr 2024 19:21:50 -0400
Subject: [PATCH 12/13] [TableGen] Ensure DAG ISel emits records when
GISelShouldIgnore'd
---
llvm/test/TableGen/simplify-patfrag.td | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/test/TableGen/simplify-patfrag.td b/llvm/test/TableGen/simplify-patfrag.td
index 904c29696a6e2c..fbb6f97f286311 100644
--- a/llvm/test/TableGen/simplify-patfrag.td
+++ b/llvm/test/TableGen/simplify-patfrag.td
@@ -1,4 +1,5 @@
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -DIGNORE %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
@@ -29,6 +30,10 @@ def anyconvert : PatFrags<(ops node:$src),
[(bitconvert node:$src),
(specialconvert node:$src)]>;
+#ifdef IGNORE
+// Ensure ShouldIgnore does not disable records in dag isel emitter
+let GISelShouldIgnore = 1 in
+#endif
// And a rule that matches that PatFrag and turns it into i2f
def : Pat<(f32 (anyconvert (i32 GPR:$val))), (i2f GPR:$val)>;
>From f13bdce29da63d704cf688bcb5ada591ae87f283 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Wed, 24 Apr 2024 19:34:14 -0400
Subject: [PATCH 13/13] [AMDGPU] GISelShouldIgnore bit to skipped Patterns
Apply the new bit to Pattern records to avoid warnings from -warn-on-skipped-patterns. This still needs formatting...
---
llvm/lib/Target/AMDGPU/BUFInstructions.td | 32 ++--
llvm/lib/Target/AMDGPU/DSInstructions.td | 26 +--
llvm/lib/Target/AMDGPU/FLATInstructions.td | 34 ++--
llvm/lib/Target/AMDGPU/SIInstructions.td | 196 ++++++++++----------
llvm/lib/Target/AMDGPU/SOPInstructions.td | 8 +-
llvm/lib/Target/AMDGPU/VOP1Instructions.td | 14 +-
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 16 +-
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 28 +--
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 10 +-
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 12 +-
10 files changed, 188 insertions(+), 188 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 273f92abf35465..cf93393f7d4c36 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -1438,28 +1438,28 @@ multiclass MUBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
string opcode, ValueType memoryVt = vt> {
defvar st = !if(!eq(memoryVt, vt), name, mubuf_intrinsic_store<name, memoryVt>);
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$auxiliary, 0),
(!cast<MUBUF_Pseudo>(opcode # _OFFSET_exact) getVregSrcForVT<vt>.ret:$vdata, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset,
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
timm:$auxiliary, 0),
(!cast<MUBUF_Pseudo>(opcode # _OFFEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
timm:$offset, (extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$auxiliary, timm),
(!cast<MUBUF_Pseudo>(opcode # _IDXEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
timm:$offset, (extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
timm:$auxiliary, timm),
(!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact)
@@ -1643,7 +1643,7 @@ multiclass SIBufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst,
(extract_cpol_set_glc $auxiliary), (extract_cpol $auxiliary));
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(vt (Op vt:$vdata_in, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset),
timm:$offset, timm:$auxiliary, 0)),
(!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
@@ -1651,7 +1651,7 @@ multiclass SIBufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst,
timm:$offset, CachePolicy)
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(vt (Op vt:$vdata_in, v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset),
timm:$offset, timm:$auxiliary, timm)),
(!cast<MUBUF_Pseudo>(Inst # "_IDXEN" # InstSuffix)
@@ -1659,7 +1659,7 @@ multiclass SIBufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst,
SCSrc_b32:$soffset, timm:$offset, CachePolicy)
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(vt (Op vt:$vdata_in, v4i32:$rsrc, 0, i32:$voffset,
(BUFSOffset i32:$soffset), timm:$offset, timm:$auxiliary, 0)),
(!cast<MUBUF_Pseudo>(Inst # "_OFFEN" # InstSuffix)
@@ -1667,7 +1667,7 @@ multiclass SIBufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst,
SCSrc_b32:$soffset, timm:$offset, CachePolicy)
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(vt (Op vt:$vdata_in, v4i32:$rsrc, i32:$vindex, i32:$voffset,
(BUFSOffset i32:$soffset), timm:$offset, timm:$auxiliary, timm)),
(!cast<MUBUF_Pseudo>(Inst # "_BOTHEN" # InstSuffix)
@@ -1907,7 +1907,7 @@ multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Ins
(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(vt (atomic_ld (MUBUFOffset v4i32:$rsrc, i32:$soffset, i32:$offset))),
(Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset))
>;
@@ -1979,12 +1979,12 @@ multiclass MUBUFScratchLoadPat <string Instr,
// XXX - Is it possible to have a complex pattern in a PatFrag?
multiclass MUBUFScratchLoadPat_D16_Common <string Instr,
ValueType vt, PatFrag ld_frag> {
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(ld_frag (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, i32:$offset), vt:$in),
(!cast<MUBUF_Pseudo>(Instr # _OFFEN) $vaddr, $srsrc, $soffset, $offset, $in)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(ld_frag (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, i32:$offset), vt:$in),
(!cast<MUBUF_Pseudo>(Instr # _OFFSET) $srsrc, $soffset, $offset, $in)
>;
@@ -2042,7 +2042,7 @@ multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo In
(Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(atomic_st vt:$val, (MUBUFOffset v4i32:$rsrc, i32:$soffset, i32:$offset)),
(Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset))
>;
@@ -2211,7 +2211,7 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
string opcode, ValueType memoryVt = vt> {
defvar st = !if(!eq(memoryVt, vt), name, mtbuf_intrinsic_store<name, memoryVt>);
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, 0),
(!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) getVregSrcForVT<vt>.ret:$vdata, SReg_128:$rsrc, SCSrc_b32:$soffset,
@@ -2219,7 +2219,7 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, timm),
(!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
@@ -2227,7 +2227,7 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, 0),
(!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
@@ -2235,7 +2235,7 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, (BUFSOffset i32:$soffset),
timm:$offset, timm:$format, timm:$auxiliary, timm),
(!cast<MTBUF_Pseudo>(opcode # _BOTHEN_exact)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 0773ef7f323418..6e37e2b9fa77b6 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -798,19 +798,19 @@ defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
let OtherPredicates = [D16PreservesUnusedBits] in {
-def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
-def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
-def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
-def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
-def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
-def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
-def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
-def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
-def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
-def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
-def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
-def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
+let GISelShouldIgnore = 1 in def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
}
class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
@@ -1148,7 +1148,7 @@ def : GCNPat <
} // End SubtargetPredicate = HasAtomicDsPkAdd16Insts
let OtherPredicates = [HasGDS] in
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(SIds_ordered_count i32:$value, i16:$offset),
(DS_ORDERED_COUNT $value, (as_i16imm $offset))
>;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 27d5616565f264..50e46651b6eeee 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -1330,19 +1330,19 @@ def : FlatStorePat <FLAT_STORE_BYTE_D16_HI, truncstorei8_hi16_flat, i32>;
}
let OtherPredicates = [D16PreservesUnusedBits] in {
-def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2f16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2f16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2f16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2f16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2f16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2i16>;
-def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2f16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2i16>;
+let GISelShouldIgnore = 1 in def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2f16>;
}
} // End OtherPredicates = [HasFlatAddressSpace]
@@ -1359,11 +1359,11 @@ multiclass GlobalFLATLoadPats<FLAT_Pseudo inst, SDPatternOperator node, ValueTyp
}
multiclass GlobalFLATLoadPats_D16<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> {
- def : FlatSignedLoadPat_D16 <inst, node, vt> {
+let GISelShouldIgnore = 1 in def : FlatSignedLoadPat_D16 <inst, node, vt> {
let AddedComplexity = 10;
}
- def : GlobalLoadSaddrPat_D16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> {
+let GISelShouldIgnore = 1 in def : GlobalLoadSaddrPat_D16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> {
let AddedComplexity = 11;
}
}
@@ -1462,15 +1462,15 @@ multiclass ScratchFLATStorePats<FLAT_Pseudo inst, SDPatternOperator node,
}
multiclass ScratchFLATLoadPats_D16<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> {
- def : ScratchLoadSignedPat_D16 <inst, node, vt> {
+let GISelShouldIgnore = 1 in def : ScratchLoadSignedPat_D16 <inst, node, vt> {
let AddedComplexity = 25;
}
- def : ScratchLoadSaddrPat_D16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> {
+let GISelShouldIgnore = 1 in def : ScratchLoadSaddrPat_D16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> {
let AddedComplexity = 26;
}
- def : ScratchLoadSVaddrPat_D16 <!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
+let GISelShouldIgnore = 1 in def : ScratchLoadSVaddrPat_D16 <!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
let SubtargetPredicate = HasFlatScratchSVSMode;
let AddedComplexity = 27;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index d6d49889656bbc..e61d82797aecf1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -628,7 +628,7 @@ def SI_CALL_ISEL : SPseudoInstSI <
let isConvergent = 1;
}
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUcall i64:$src0, (i64 0)),
(SI_CALL_ISEL $src0, (i64 0))
>;
@@ -666,13 +666,13 @@ def SI_TCRETURN : SI_TCRETURN_Pseudo<CCR_SGPR_64, AMDGPUtc_return>;
def SI_TCRETURN_GFX : SI_TCRETURN_Pseudo<Gfx_CCR_SGPR_64, AMDGPUtc_return_gfx>;
// Handle selecting indirect tail calls
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUtc_return i64:$src0, (i64 0), (i32 timm:$fpdiff)),
(SI_TCRETURN CCR_SGPR_64:$src0, (i64 0), i32imm:$fpdiff)
>;
// Handle selecting indirect tail calls for AMDGPU_gfx
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUtc_return_gfx i64:$src0, (i64 0), (i32 timm:$fpdiff)),
(SI_TCRETURN_GFX Gfx_CCR_SGPR_64:$src0, (i64 0), i32imm:$fpdiff)
>;
@@ -703,7 +703,7 @@ def SI_CS_CHAIN_TC_W64 : SI_CS_CHAIN_TC<i64, isWave64>;
// Handle selecting direct & indirect calls via SI_CS_CHAIN_TC_W32/64
multiclass si_cs_chain_tc_pattern<
dag callee, ValueType execvt, RegisterOperand execrc, Instruction tc> {
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUtc_return_chain i64:$src0, callee, (i32 timm:$fpdiff), execvt:$exec),
(tc CCR_SGPR_64:$src0, callee, i32imm:$fpdiff, execrc:$exec)
>;
@@ -1045,17 +1045,17 @@ def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
let Defs = [SCC];
}
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(SIpc_add_rel_offset tglobaladdr:$ptr_lo, 0),
(SI_PC_ADD_REL_OFFSET $ptr_lo, (i32 0))
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUtrap timm:$trapid),
(S_TRAP $trapid)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(AMDGPUelse i1:$src, bb:$target),
(SI_ELSE $src, $target)
>;
@@ -1070,7 +1070,7 @@ def : Pat <
(SI_KILL_I1_PSEUDO SCSrc_i1:$src, -1)
>;
-def : Pat <
+let GISelShouldIgnore = 1 in def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineImmFP32:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO VSrc_b32:$src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
>;
@@ -1087,12 +1087,12 @@ def : Pat <
// TODO: we could add more variants for other types of conditionals
-def : Pat <
+let GISelShouldIgnore = 1 in def : Pat <
(i64 (int_amdgcn_icmp i1:$src, (i1 0), (i32 33))),
(COPY $src) // Return the SGPRs representing i1 src
>;
-def : Pat <
+let GISelShouldIgnore = 1 in def : Pat <
(i32 (int_amdgcn_icmp i1:$src, (i1 0), (i32 33))),
(COPY $src) // Return the SGPRs representing i1 src
>;
@@ -1103,38 +1103,38 @@ def : Pat <
multiclass f16_fp_Pats<Instruction cvt_f16_f32_inst_e64, Instruction cvt_f32_f16_inst_e64> {
// f16_to_fp patterns
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (any_f16_to_fp i32:$src0)),
(cvt_f32_f16_inst_e64 SRCMODS.NONE, $src0)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
(cvt_f32_f16_inst_e64 SRCMODS.ABS, $src0)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (f16_to_fp (i32 (srl_oneuse (and_oneuse i32:$src0, 0x7fff0000), (i32 16))))),
(cvt_f32_f16_inst_e64 SRCMODS.ABS, (i32 (V_LSHRREV_B32_e64 (i32 16), i32:$src0)))
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))),
(cvt_f32_f16_inst_e64 SRCMODS.NEG_ABS, $src0)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (f16_to_fp (xor_oneuse i32:$src0, 0x8000))),
(cvt_f32_f16_inst_e64 SRCMODS.NEG, $src0)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f64 (any_fpextend f16:$src)),
(V_CVT_F64_F32_e32 (cvt_f32_f16_inst_e64 SRCMODS.NONE, $src))
>;
// fp_to_fp16 patterns
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (AMDGPUfp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(cvt_f16_f32_inst_e64 $src0_modifiers, f32:$src0)
>;
@@ -1161,7 +1161,7 @@ multiclass f16_fp_Pats<Instruction cvt_f16_f32_inst_e64, Instruction cvt_f32_f16
// This is only used on targets without half support
// TODO: Introduce strict variant of AMDGPUfp_to_f16 and share custom lowering
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (strict_fp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(cvt_f16_f32_inst_e64 $src0_modifiers, f32:$src0)
>;
@@ -1190,13 +1190,13 @@ class FMADPat <ValueType vt, Instruction inst>
// Prefer mac form when there are no modifiers.
let AddedComplexity = 9 in {
let OtherPredicates = [HasMadMacF32Insts] in
-def : FMADPat <f32, V_MAC_F32_e64>;
+let GISelShouldIgnore = 1 in def : FMADPat <f32, V_MAC_F32_e64>;
// Don't allow source modifiers. If there are any source modifiers then it's
// better to select mad instead of mac.
let SubtargetPredicate = isGFX6GFX7GFX10,
OtherPredicates = [HasMadMacF32Insts, NoFP32Denormals] in
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (fadd (AMDGPUfmul_legacy (VOP3NoMods f32:$src0),
(VOP3NoMods f32:$src1)),
(VOP3NoMods f32:$src2))),
@@ -1216,11 +1216,11 @@ def : GCNPat <
>;
let SubtargetPredicate = Has16BitInsts in
-def : FMADPat <f16, V_MAC_F16_e64>;
+let GISelShouldIgnore = 1 in def : FMADPat <f16, V_MAC_F16_e64>;
} // AddedComplexity = 9
let OtherPredicates = [HasMadMacF32Insts, NoFP32Denormals] in
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f32 (fadd (AMDGPUfmul_legacy (VOP3Mods f32:$src0, i32:$src0_mod),
(VOP3Mods f32:$src1, i32:$src1_mod)),
(VOP3Mods f32:$src2, i32:$src2_mod))),
@@ -1246,7 +1246,7 @@ def : VOPSelectPat <f16>;
def : VOPSelectPat <i16>;
let AddedComplexity = 1 in {
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (add (i32 (DivergentUnaryFrag<ctpop> i32:$popcnt)), i32:$val)),
(V_BCNT_U32_B32_e64 $popcnt, $val)
>;
@@ -1257,12 +1257,12 @@ def : GCNPat <
(V_BCNT_U32_B32_e64 VSrc_b32:$popcnt, (i32 0))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (add (i16 (trunc (i32 (DivergentUnaryFrag<ctpop> i32:$popcnt)))), i16:$val)),
(V_BCNT_U32_B32_e64 $popcnt, $val)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentUnaryFrag<ctpop> i64:$src)),
(REG_SEQUENCE VReg_64,
(V_BCNT_U32_B32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub1)),
@@ -1277,12 +1277,12 @@ def : GCNPat <
// Special case for 2 element vectors. REQ_SEQUENCE produces better code
// than an INSERT_SUBREG.
multiclass Insert_Element_V2<RegisterClass RC, ValueType elem_type, ValueType vec_type> {
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(insertelt vec_type:$vec, elem_type:$elem, 0),
(REG_SEQUENCE RC, $elem, sub0, (elem_type (EXTRACT_SUBREG $vec, sub1)), sub1)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(insertelt vec_type:$vec, elem_type:$elem, 1),
(REG_SEQUENCE RC, (elem_type (EXTRACT_SUBREG $vec, sub0)), sub0, $elem, sub1)
>;
@@ -1944,7 +1944,7 @@ def : GCNPat <
// COPY_TO_REGCLASS is needed to avoid using SCC from S_XOR_B32 instead
// of the real value.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(UniformUnaryFrag<fneg> (v2f32 SReg_64:$src)),
(v2f32 (REG_SEQUENCE SReg_64,
(f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
@@ -1955,7 +1955,7 @@ def : GCNPat <
SReg_32)), sub1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(UniformUnaryFrag<fabs> (v2f32 SReg_64:$src)),
(v2f32 (REG_SEQUENCE SReg_64,
(f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
@@ -1966,7 +1966,7 @@ def : GCNPat <
SReg_32)), sub1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(UniformUnaryFrag<fneg> (fabs (v2f32 SReg_64:$src))),
(v2f32 (REG_SEQUENCE SReg_64,
(f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
@@ -2106,7 +2106,7 @@ def : GCNPat <
(V_LSHLREV_B32_e64 (i32 16), $src1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(fcopysign f64:$src0, fp16vt:$src1),
(REG_SEQUENCE SReg_64,
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
@@ -2120,7 +2120,7 @@ def : GCNPat <
(V_LSHRREV_B32_e64 (i32 16), $src1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(fcopysign fp16vt:$src0, f64:$src1),
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0,
(V_LSHRREV_B32_e64 (i32 16), (EXTRACT_SUBREG $src1, sub1)))
@@ -2131,12 +2131,12 @@ def : GCNPat <
/********** Immediate Patterns **********/
/********** ================== **********/
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(i32 imm)>:$imm),
(V_MOV_B32_e32 imm:$imm)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(f32 fpimm)>:$imm),
(V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
>;
@@ -2146,12 +2146,12 @@ def : GCNPat <
(S_MOV_B32 imm:$imm)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(SIlds tglobaladdr:$ga)>),
(V_MOV_B32_e32 $ga)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(SIlds tglobaladdr:$ga),
(S_MOV_B32 $ga)
>;
@@ -2159,12 +2159,12 @@ def : GCNPat <
// FIXME: Workaround for ordering issue with peephole optimizer where
// a register class copy interferes with immediate folding. Should
// use s_mov_b32, which can be shrunk to s_movk_i32
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(f16 fpimm)>:$imm),
(V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm)))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(bf16 fpimm)>:$imm),
(V_MOV_B32_e32 (bf16 (bitcast_fpimm_to_i32 $imm)))
>;
@@ -2172,12 +2172,12 @@ def : GCNPat <
// V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO can be used with any 64-bit
// immediate and wil be expanded as needed, but we will only use these patterns
// for values which can be encoded.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(i64 imm)>:$imm),
(V_MOV_B64_PSEUDO imm:$imm)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(VGPRImm<(f64 fpimm)>:$imm),
(V_MOV_B64_PSEUDO (f64 (bitcast_fpimm_to_i64 $imm)))
>;
@@ -2187,7 +2187,7 @@ def : GCNPat <
(S_MOV_B64_IMM_PSEUDO imm:$imm)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f64 fpimm:$imm),
(S_MOV_B64_IMM_PSEUDO (i64 (bitcast_fpimm_to_i64 fpimm:$imm)))
>;
@@ -2225,21 +2225,21 @@ def : GCNPat <
// XXX - Should this use a s_cmp to set SCC?
// Set to sign-extended 64-bit value (true = -1, false = 0)
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 imm:$imm),
(S_MOV_B64 (i64 (as_i64imm $imm)))
> {
let WaveSizePredicate = isWave64;
}
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 imm:$imm),
(S_MOV_B32 (i32 (as_i32imm $imm)))
> {
let WaveSizePredicate = isWave32;
}
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(f64 InlineImmFP64:$imm),
(S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineImmFP64:$imm)))
>;
@@ -2270,7 +2270,7 @@ def : Ext32Pat <anyext>;
// The multiplication scales from [0,1) to the unsigned integer range,
// rounding down a bit to avoid unwanted overflow.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(AMDGPUurecip i32:$src0),
(V_CVT_U32_F32_e32
(V_MUL_F32_e32 (i32 CONST.FP_4294966784),
@@ -2281,8 +2281,8 @@ def : GCNPat <
// VOP3 Patterns
//===----------------------------------------------------------------------===//
-def : IMad24Pat<V_MAD_I32_I24_e64, 1>;
-def : UMad24Pat<V_MAD_U32_U24_e64, 1>;
+let GISelShouldIgnore = 1 in def : IMad24Pat<V_MAD_I32_I24_e64, 1>;
+let GISelShouldIgnore = 1 in def : UMad24Pat<V_MAD_U32_U24_e64, 1>;
// BFI patterns
@@ -2308,7 +2308,7 @@ def : AMDGPUPatIgnoreCopies <
>;
// (y & C) | (z & ~C)
-def : AMDGPUPatIgnoreCopies <
+let GISelShouldIgnore = 1 in def : AMDGPUPatIgnoreCopies <
(BFIImm32 i32:$x, i32:$y, i32:$z),
(V_BFI_B32_e64 VSrc_b32:$x, VSrc_b32:$y, VSrc_b32:$z)
>;
@@ -2357,7 +2357,7 @@ def : AMDGPUPat <
(i32 (EXTRACT_SUBREG SReg_64:$src1, sub1)))
>;
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(fcopysign f64:$src0, f64:$src1),
(REG_SEQUENCE SReg_64,
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
@@ -2366,7 +2366,7 @@ def : AMDGPUPat <
(i32 (EXTRACT_SUBREG SReg_64:$src1, sub1))), sub1)
>;
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(fcopysign f64:$src0, f32:$src1),
(REG_SEQUENCE SReg_64,
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
@@ -2377,11 +2377,11 @@ def : AMDGPUPat <
def : ROTRPattern <V_ALIGNBIT_B32_e64>;
-def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
+let GISelShouldIgnore = 1 in def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
-def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
+let GISelShouldIgnore = 1 in def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
@@ -2391,13 +2391,13 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
// Extract with offset
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
(!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
>;
// Insert with offset
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
(!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
>;
@@ -2427,14 +2427,14 @@ defm : SI_INDIRECT_Pattern <v32i32, i32, "V32">;
// SAD Patterns
//===----------------------------------------------------------------------===//
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(add (sub_oneuse (umax i32:$src0, i32:$src1),
(umin i32:$src0, i32:$src1)),
i32:$src2),
(V_SAD_U32_e64 $src0, $src1, $src2, (i1 0))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
(sub i32:$src0, i32:$src1),
(sub i32:$src1, i32:$src0)),
@@ -2445,86 +2445,86 @@ def : GCNPat <
//===----------------------------------------------------------------------===//
// Conversion Patterns
//===----------------------------------------------------------------------===//
-def : GCNPat<(i32 (UniformSextInreg<i1> i32:$src)),
+let GISelShouldIgnore = 1 in def : GCNPat<(i32 (UniformSextInreg<i1> i32:$src)),
(S_BFE_I32 i32:$src, (i32 65536))>; // 0 | 1 << 16
// Handle sext_inreg in i64
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (UniformSextInreg<i1> i64:$src)),
(S_BFE_I64 i64:$src, (i32 0x10000)) // 0 | 1 << 16
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (UniformSextInreg<i1> i16:$src)),
(S_BFE_I32 $src, (i32 0x00010000)) // 0 | 1 << 16
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (UniformSextInreg<i8> i16:$src)),
(S_BFE_I32 $src, (i32 0x80000)) // 0 | 8 << 16
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (UniformSextInreg<i8> i64:$src)),
(S_BFE_I64 i64:$src, (i32 0x80000)) // 0 | 8 << 16
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (UniformSextInreg<i16> i64:$src)),
(S_BFE_I64 i64:$src, (i32 0x100000)) // 0 | 16 << 16
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (UniformSextInreg<i32> i64:$src)),
(S_BFE_I64 i64:$src, (i32 0x200000)) // 0 | 32 << 16
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (DivergentSextInreg<i1> i32:$src)),
(V_BFE_I32_e64 i32:$src, (i32 0), (i32 1))>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (DivergentSextInreg<i1> i16:$src)),
(V_BFE_I32_e64 $src, (i32 0), (i32 1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (DivergentSextInreg<i8> i16:$src)),
(V_BFE_I32_e64 $src, (i32 0), (i32 8))
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (DivergentSextInreg<i8> i32:$src)),
(V_BFE_I32_e64 i32:$src, (i32 0), (i32 8))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (DivergentSextInreg<i16> i32:$src)),
(V_BFE_I32_e64 $src, (i32 0), (i32 16))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentSextInreg<i1> i64:$src)),
(REG_SEQUENCE VReg_64,
(V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 1)), sub0,
(V_ASHRREV_I32_e32 (i32 31), (V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 1))), sub1)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentSextInreg<i8> i64:$src)),
(REG_SEQUENCE VReg_64,
(V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 8)), sub0,
(V_ASHRREV_I32_e32 (i32 31), (V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 8))), sub1)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentSextInreg<i16> i64:$src)),
(REG_SEQUENCE VReg_64,
(V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 16)), sub0,
(V_ASHRREV_I32_e32 (i32 31), (V_BFE_I32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0), (i32 16))), sub1)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentSextInreg<i32> i64:$src)),
(REG_SEQUENCE VReg_64,
(i32 (EXTRACT_SUBREG i64:$src, sub0)), sub0,
@@ -2686,7 +2686,7 @@ def : GCNPat <
(V_NOT_B32_e32 $src0)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (DivergentBinFrag<xor> i64:$src0, (i64 -1))),
(REG_SEQUENCE VReg_64,
(V_NOT_B32_e32 (i32 (EXTRACT_SUBREG i64:$src0, sub0))), sub0,
@@ -2794,26 +2794,26 @@ def : GCNPat<
(S_MOV_B32 (i32 0)), sub1)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (zext (i16 (bitconvert fp16_zeros_high_16bits:$src)))),
(COPY VSrc_b16:$src)>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (trunc i64:$a)),
(EXTRACT_SUBREG $a, sub0)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (UniformUnaryFrag<trunc> i32:$a)),
(S_CMP_EQ_U32 (S_AND_B32 (i32 1), $a), (i32 1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (UniformUnaryFrag<trunc> i16:$a)),
(S_CMP_EQ_U32 (S_AND_B32 (i32 1), $a), (i32 1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (UniformUnaryFrag<trunc> i64:$a)),
(S_CMP_EQ_U32 (S_AND_B32 (i32 1),
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
@@ -2844,20 +2844,20 @@ def IMMBitSelConst : SDNodeXForm<imm, [{
// v_cmp_ne_u32_e64 $a, 0, $a
// Handle the VALU case.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (DivergentUnaryFrag<trunc> (i32 (srl i32:$a, (i32 imm:$b))))),
(V_CMP_NE_U32_e64 (V_AND_B32_e64 (i32 (IMMBitSelConst $b)), $a),
(i32 0))
>;
// Handle the scalar case.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (UniformUnaryFrag<trunc> (i32 (srl i32:$a, (i32 imm:$b))))),
(S_CMP_LG_U32 (S_AND_B32 (i32 (IMMBitSelConst $b)), $a),
(i32 0))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i1 (DivergentUnaryFrag<trunc> i64:$a)),
(V_CMP_EQ_U32_e64 (V_AND_B32_e64 (i32 1),
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
@@ -2947,7 +2947,7 @@ def : GCNPat<
// If fcanonicalize's operand is implicitly canonicalized, we only need a copy.
let AddedComplexity = 1000 in {
foreach vt = [f16, v2f16, f32, v2f32, f64] in {
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(fcanonicalize (vt is_canonicalized:$src)),
(COPY vt:$src)
>;
@@ -3146,12 +3146,12 @@ def : GCNPat <
(v2i16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), VGPR_32:$src1))
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v2f16 (UniformBinFrag<build_vector> (f16 SReg_32:$src1), (f16 FP_ZERO))),
(S_AND_B32 (S_MOV_B32 (i32 0xffff)), SReg_32:$src1)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v2f16 (DivergentBinFrag<build_vector> (f16 VGPR_32:$src1), (f16 FP_ZERO))),
(v2f16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), VGPR_32:$src1))
>;
@@ -3166,7 +3166,7 @@ def : GCNPat <
(COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v2f16 (build_vector f16:$src0, (f16 undef))),
(COPY $src0)
>;
@@ -3238,7 +3238,7 @@ def : GCNPat <
// Take the lower 16 bits from V[0] and the upper 16 bits from V[1]
// Special case, can use V_BFI (0xffff literal likely more reusable than 0x70601000)
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(vecTy (DivergentBinFrag<build_vector> (Ty (immzeroTy)),
(Ty !if(!eq(Ty, i16),
(Ty (trunc (srl VGPR_32:$b, (i32 16)))),
@@ -3303,22 +3303,22 @@ def : GCNPat <
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v2f16 (scalar_to_vector f16:$src0)),
(COPY $src0)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v2i16 (scalar_to_vector i16:$src0)),
(COPY $src0)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v4i16 (scalar_to_vector i16:$src0)),
(INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(v4f16 (scalar_to_vector f16:$src0)),
(INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
>;
@@ -3410,12 +3410,12 @@ def : GCNPat<
>;
multiclass BFMPatterns <ValueType vt, PatFrag SHL, PatFrag ADD, InstSI BFM> {
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(vt (SHL (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
(BFM $a, $b)
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(vt (ADD (vt (shl 1, vt:$a)), -1)),
(BFM $a, (i32 0))
>;
@@ -3436,39 +3436,39 @@ def IMMPopCount : SDNodeXForm<imm, [{
MVT::i32);
}]>;
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<and> (i32 (srl i32:$src, i32:$rshift)),
IMMZeroBasedBitfieldMask:$mask),
(V_BFE_U32_e64 $src, $rshift, (i32 (IMMPopCount $mask)))
>;
// x & ((1 << y) - 1)
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<and> i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)),
(V_BFE_U32_e64 $src, (i32 0), $width)
>;
// x & ~(-1 << y)
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<and> i32:$src,
(xor_oneuse (shl_oneuse -1, i32:$width), -1)),
(V_BFE_U32_e64 $src, (i32 0), $width)
>;
// x & (-1 >> (bitwidth - y))
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<and> i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),
(V_BFE_U32_e64 $src, (i32 0), $width)
>;
// x << (bitwidth - y) >> (bitwidth - y)
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<srl> (shl_oneuse i32:$src, (sub 32, i32:$width)),
(sub 32, i32:$width)),
(V_BFE_U32_e64 $src, (i32 0), $width)
>;
-def : AMDGPUPat <
+let GISelShouldIgnore = 1 in def : AMDGPUPat <
(DivergentBinFrag<sra> (shl_oneuse i32:$src, (sub 32, i32:$width)),
(sub 32, i32:$width)),
(V_BFE_I32_e64 $src, (i32 0), $width)
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 0b7d45ee8c027d..663cfa3070c8ab 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1767,7 +1767,7 @@ let OtherPredicates = [HasExportInsts] in
// SOP1 Patterns
//===----------------------------------------------------------------------===//
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(AMDGPUendpgm),
(S_ENDPGM (i16 0))
>;
@@ -1876,7 +1876,7 @@ def UniformSelect : PatFrag<
>;
let AddedComplexity = 20 in {
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (UniformSelect i32:$src0, i32:$src1)),
(S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)
>;
@@ -1884,7 +1884,7 @@ let AddedComplexity = 20 in {
// TODO: The predicate should not be necessary, but enabling this pattern for
// all subtargets generates worse code in some cases.
let OtherPredicates = [HasPseudoScalarTrans] in
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(f32 (UniformSelect f32:$src0, f32:$src1)),
(S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)
>;
@@ -1892,7 +1892,7 @@ let AddedComplexity = 20 in {
// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
// case, the sgpr-copies pass will fix this to use the vector version.
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (addc i32:$src0, i32:$src1)),
(S_ADD_U32 $src0, $src1)
>;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 2341e0d9d32bb4..c9fc3fbcee5378 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -498,21 +498,21 @@ defm V_FRACT_F16 : VOP1Inst_t16 <"v_fract_f16", VOP_F16_F16, AMDGPUfract>;
} // End FPDPRounding = 1
let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(f32 (f16_to_fp i16:$src)),
(V_CVT_F32_F16_e32 $src)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i16 (AMDGPUfp_to_f16 f32:$src)),
(V_CVT_F16_F32_e32 $src)
>;
}
let OtherPredicates = [HasTrue16BitInsts] in {
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(f32 (f16_to_fp i16:$src)),
(V_CVT_F32_F16_t16_e32 $src)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i16 (AMDGPUfp_to_f16 f32:$src)),
(V_CVT_F16_F32_t16_e32 $src)
>;
@@ -1358,7 +1358,7 @@ def : UpdateDPPPat<v2f16>;
} // End OtherPredicates = [isGFX8Plus]
let OtherPredicates = [isGFX8Plus] in {
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (anyext i16:$src)),
(COPY $src)
>;
@@ -1370,12 +1370,12 @@ def : GCNPat<
(V_MOV_B32_e32 (i32 0)), sub1)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i16 (trunc i32:$src)),
(COPY $src)
>;
-def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i16 (trunc i64:$src)),
(EXTRACT_SUBREG $src, sub0)
>;
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index c001c5de81e0b7..450866889b3d84 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -885,8 +885,8 @@ class mul24_64_Pat<SDPatternOperator Op, Instruction InstLo, Instruction InstHi>
(InstHi $src0, $src1), sub1)
>;
-def : mul24_64_Pat<AMDGPUmul_i24, V_MUL_I32_I24_e64, V_MUL_HI_I32_I24_e64>;
-def : mul24_64_Pat<AMDGPUmul_u24, V_MUL_U32_U24_e64, V_MUL_HI_U32_U24_e64>;
+let GISelShouldIgnore = 1 in def : mul24_64_Pat<AMDGPUmul_i24, V_MUL_I32_I24_e64, V_MUL_HI_I32_I24_e64>;
+let GISelShouldIgnore = 1 in def : mul24_64_Pat<AMDGPUmul_u24, V_MUL_U32_U24_e64, V_MUL_HI_U32_U24_e64>;
//===----------------------------------------------------------------------===//
// 16-Bit Operand Instructions
@@ -1020,17 +1020,17 @@ let SubtargetPredicate = HasDLInsts in {
let isReMaterializable = 1 in
defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (DivergentUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1))),
(i32 (V_XNOR_B32_e64 $src0, $src1))
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i32 (DivergentBinFrag<xor_oneuse> (not i32:$src0), i32:$src1)),
(i32 (V_XNOR_B32_e64 $src0, $src1))
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i64 (DivergentUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1))),
(REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64
(i32 (EXTRACT_SUBREG $src0, sub0)),
@@ -1040,7 +1040,7 @@ def : GCNPat<
(i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i64 (DivergentBinFrag<xor_oneuse> (not i64:$src0), i64:$src1)),
(REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64
(i32 (EXTRACT_SUBREG $src0, sub0)),
@@ -1092,7 +1092,7 @@ let Constraints = "$vdst = $src2",
}
let AddedComplexity = 30 in {
- def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
(f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
> {
@@ -1138,7 +1138,7 @@ def : GCNPat<
(inst VSrc_b16:$src0, VSrc_b16:$src1)
>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(i64 (zext (op i16:$src0, i16:$src1))),
(REG_SEQUENCE VReg_64,
(inst $src0, $src1), sub0,
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 647595d9ccab30..739d3ecbc7f2b6 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -442,7 +442,7 @@ class Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2,
>;
let Predicates = [Has16BitInsts, isGFX10Plus] in {
-def: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64>;
+let GISelShouldIgnore = 1 in def: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64>;
} // End Predicates = [Has16BitInsts, isGFX10Plus]
class ThreeOpFragSDAG<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
@@ -694,7 +694,7 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>;
def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>;
def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>;
-def : GCNPat<
+let GISelShouldIgnore = 1 in def : GCNPat<
(DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
(V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
@@ -707,7 +707,7 @@ def : GCNPat<
def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>;
def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>;
-def : GCNPat<(DivergentBinFrag<or> (or_oneuse i64:$src0, i64:$src1), i64:$src2),
+let GISelShouldIgnore = 1 in def : GCNPat<(DivergentBinFrag<or> (or_oneuse i64:$src0, i64:$src1), i64:$src2),
(REG_SEQUENCE VReg_64,
(V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)),
(i32 (EXTRACT_SUBREG $src1, sub0)),
@@ -753,7 +753,7 @@ multiclass IMAD32_Pats <VOP3_Pseudo inst> {
// Immediate src2 in the pattern above will not fold because it would be partially
// undef. Hence define specialized pattern for this case.
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(ThreeOpFrag<mul, add> i32:$src0, i32:$src1, (i32 imm:$src2)),
(EXTRACT_SUBREG (inst i32:$src0, i32:$src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0)
>;
@@ -769,11 +769,11 @@ class IMAD32_Mul24_Pat<VOP3_Pseudo inst>: GCNPat <
// exclude pre-GFX9 where it was slow
let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in {
defm : IMAD32_Pats<V_MAD_U64_U32_e64>;
- def : IMAD32_Mul24_Pat<V_MAD_U64_U32_e64>;
+let GISelShouldIgnore = 1 in def : IMAD32_Mul24_Pat<V_MAD_U64_U32_e64>;
}
let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in {
defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>;
- def : IMAD32_Mul24_Pat<V_MAD_U64_U32_gfx11_e64>;
+let GISelShouldIgnore = 1 in def : IMAD32_Mul24_Pat<V_MAD_U64_U32_gfx11_e64>;
}
def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
@@ -868,13 +868,13 @@ class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
>;
let WaveSizePredicate = isWave64 in {
-def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>;
-def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>;
+let GISelShouldIgnore = 1 in def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>;
+let GISelShouldIgnore = 1 in def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>;
}
let WaveSizePredicate = isWave32 in {
-def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>;
-def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>;
+let GISelShouldIgnore = 1 in def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>;
+let GISelShouldIgnore = 1 in def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>;
}
class VOP3_DOT_Profile<VOPProfile P> : VOP3_Profile<P, VOP3_OPSEL> {
@@ -945,8 +945,8 @@ class PseudoScalarPatF16<SDPatternOperator node, VOP3_Pseudo inst> : GCNPat <
let SubtargetPredicate = HasPseudoScalarTrans in {
def : PseudoScalarPatF16<AMDGPUexpf16, V_S_EXP_F16_e64>;
def : PseudoScalarPatF16<AMDGPUlogf16, V_S_LOG_F16_e64>;
- def : PseudoScalarPatF16<AMDGPUrcp, V_S_RCP_F16_e64>;
- def : PseudoScalarPatF16<AMDGPUrsq, V_S_RSQ_F16_e64>;
+let GISelShouldIgnore = 1 in def : PseudoScalarPatF16<AMDGPUrcp, V_S_RCP_F16_e64>;
+let GISelShouldIgnore = 1 in def : PseudoScalarPatF16<AMDGPUrsq, V_S_RSQ_F16_e64>;
def : PseudoScalarPatF16<any_amdgcn_sqrt, V_S_SQRT_F16_e64>;
}
@@ -977,8 +977,8 @@ class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat<
getClampRes<inst.Pfl, inst>.ret
>;
-def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>;
-def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>;
+let GISelShouldIgnore = 1 in def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>;
+let GISelShouldIgnore = 1 in def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>;
def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>;
def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index a7d63fdb2e04c8..1ccff8e663d31d 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -487,19 +487,19 @@ defm V_DOT4_F32_FP8_FP8 : VOP3PDOTF8Inst<"v_dot4_f32_fp8_fp8", int_amdgcn_dot4_f
defm V_DOT4_F32_BF8_BF8 : VOP3PDOTF8Inst<"v_dot4_f32_bf8_bf8", int_amdgcn_dot4_f32_bf8_bf8>;
}
-def : UDot2Pat<V_DOT2_U32_U16>;
-def : SDot2Pat<V_DOT2_I32_I16>;
+let GISelShouldIgnore = 1 in def : UDot2Pat<V_DOT2_U32_U16>;
+let GISelShouldIgnore = 1 in def : SDot2Pat<V_DOT2_I32_I16>;
foreach Type = ["U", "I"] in
let Predicates = !cast<VOP_Pseudo>("V_DOT4_"#Type#"32_"#Type#8).Predicates in
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
!cast<dag>(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y,
(add_oneuse lhs, (!cast<PatFrag>("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))),
(!cast<VOP3P_Pseudo>("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>;
foreach Type = ["U", "I"] in
let Predicates = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).Predicates in
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
!cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)),
[1, 2, 3, 4, 5, 6, 7], lhs, y,
(NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))),
@@ -509,7 +509,7 @@ foreach Type = ["U", "I"] in
// in the compile time. Directly handle the pattern generated by the FE here.
foreach Type = ["U", "I"] in
let Predicates = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).Predicates in
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
!cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)),
[7, 1, 2, 3, 4, 5, 6], lhs, y,
(NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))),
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 0b3a3d5321bd3b..c6eea22056e61d 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -989,19 +989,19 @@ defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
let WaveSizePredicate = isWave64 in
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
(i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))
>;
let WaveSizePredicate = isWave32 in {
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
(i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))
>;
// Support codegen of i64 setcc in wave32 mode.
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
(i64 (REG_SEQUENCE SReg_64, (inst $src0, $src1), sub0, (S_MOV_B32 (i32 0)), sub1))
>;
@@ -1058,7 +1058,7 @@ defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;
multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
let WaveSizePredicate = isWave64 in
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
(i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
@@ -1066,14 +1066,14 @@ multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
>;
let WaveSizePredicate = isWave32 in {
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
(i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
DSTCLAMP.NONE), SReg_32))
>;
- def : GCNPat <
+let GISelShouldIgnore = 1 in def : GCNPat <
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
(i64 (REG_SEQUENCE SReg_64, (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
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