[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

sdesmalen-arm wrote:

> I guess my point more widely was that when choosing a different calling convention (other than the one we currently implement), the choice of PN8 may not be right.

It seems that PTRUE (predicate-as-counter) can only use PN8-PN15, so I guess we can't use any of the other registers. So the choice of always using PN8 for this purpose is always fine, which depending on the calling convention may result in an extra callee-save spill/fill. Perhaps I'm just overcomplicating it, but it feels a bit wrong to hard-code a register like that if we have TableGen support many different calling conventions.

It would probably be useful to add an assert to make sure that PN8/P8 is not a reserved register though.

https://github.com/llvm/llvm-project/pull/77665