[llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> > Mask load/store. Their SEW are always 1.
> 
> Could we make `VSEW` also support SEW=1 scenario?

Then we will need 3 bits to encode VSEW in TSFlags. Maybe we can do it in this way:
* Remove `HasImplictSEW` field.
* Extend `VSEW` to 3 bits:
  * 0 means explicit `SEW` in operands.
  * 1-5 mean `SEW` is 1, 8, 16, 32, 64.

https://github.com/llvm/llvm-project/pull/90396