[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

momchil-velikov wrote:

> I'd also suggest wrapping the `AFI->getPredicateRegForFillSpill() != 0` in a function like `canUseMultiVectorLoadStore` (feel free to pick a different name) that combines it with `&& (Subtarget.hasSVE2p1() || Subtarget.hasSME2())`, to keep the logic in other places a bit simpler.

It should not need to combine it, since  `!(Subtarget.hasSVE2p1() || Subtarget.hasSME2())` must imply `AFI->getPredicateRegForFillSpill()  == 0`, i.e.  we don't go through the trouble of choosing a register if there's no chance for using it.

Otherwise, yes
>  * everywhere else we use only `AFI->getPredicateRegForFillSpill() != 0` as the condition determining we can and should load/store in pairs


https://github.com/llvm/llvm-project/pull/77665