[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -3072,54 +3094,65 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
       std::swap(FrameIdxReg1, FrameIdxReg2);
     }
 
-    unsigned PairRegs;
-    unsigned PnReg;
     if (RPI.isPaired() && RPI.isScalable()) {
-      PairRegs = AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0);
+      unsigned PairRegs = AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0);
+      unsigned PnReg;
       if (!PtrueCreated) {
         PtrueCreated = true;
-        PnReg = AArch64::PN8;
+        AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+        PnReg = AFI->getPredicateRegForFillSpill();
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momchil-velikov wrote:

`PnReg` is declared inside the loop and used uninitialized in every iteration, except in the first one that sets `PtrueCreated` to `true`.


https://github.com/llvm/llvm-project/pull/77665