[llvm] [AArch64][SVE2] SVE2 NBSL instruction lowering. (PR #89732)

[David Green via llvm-commits]

================
@@ -41,3 +41,18 @@ define <vscale x 4 x i32> @no_bsl_fold(<vscale x 4 x i32> %a, <vscale x 4 x i32>
   %c = or <vscale x 4 x i32> %1, %2
   ret <vscale x 4 x i32> %c
 }
+
+define <vscale x 4 x i32> @nbsl(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
----------------
davemgreen wrote:

It is probably worth having a test per type-size, if the patterns are different.

https://github.com/llvm/llvm-project/pull/89732