[llvm] [RISCV] Use the store value's VT as the MemoryVT after combining riscv.masked.strided.store (PR #89874)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/89874

According to `RISCVTargetLowering::getTgtMemIntrinsic`, the MemoryVT
is the scalar element VT for strided store and the MemoryVT is the
same as the store value's VT for unit-stride store.

After combining `riscv.masked.strided.store` to `masked.store`, we
just use the scalar element VT to construct `masked.store`, which is
wrong.

With wrong MemoryVT, the DAGCombiner will combine `trunc+masked.store`
to truncated `masked.store` because `TLI.canCombineTruncStore` returns
true.

So, we should use the store value's VT as the MemoryVT.

This fixes #89833.



>From 091de698a61e8120a850e81b673bbbd94505e4cf Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 24 Apr 2024 13:26:11 +0800
Subject: [PATCH 1/2] [RISCV] Add precommit test

---
 llvm/test/CodeGen/RISCV/pr89833.ll | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/pr89833.ll

diff --git a/llvm/test/CodeGen/RISCV/pr89833.ll b/llvm/test/CodeGen/RISCV/pr89833.ll
new file mode 100644
index 00000000000000..de3b5e27838623
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr89833.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
+
+declare void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr, i64, <vscale x 16 x i1>)
+
+define void @test(<vscale x 16 x i16> %value, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vse16.v v8, (zero), v0.t
+; CHECK-NEXT:    ret
+  %trunc = trunc <vscale x 16 x i16> %value to <vscale x 16 x i8>
+  call void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8> %trunc, ptr null, i64 1, <vscale x 16 x i1> %mask)
+  ret void
+}

>From 0ae5304e441b42b1f8561cdbadc1910d16b0c5c7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 24 Apr 2024 13:29:03 +0800
Subject: [PATCH 2/2] [RISCV] Use the store value's VT as the MemoryVT after
 combining riscv.masked.strided.store

According to `RISCVTargetLowering::getTgtMemIntrinsic`, the MemoryVT
is the scalar element VT for strided store and the MemoryVT is the
same as the store value's VT for unit-stride store.

After combining `riscv.masked.strided.store` to `masked.store`, we
just use the scalar element VT to construct `masked.store`, which is
wrong.

With wrong MemoryVT, the DAGCombiner will combine `trunc+masked.store`
to truncated `masked.store` because `TLI.canCombineTruncStore` returns
true.

So, we should use the store value's VT as the MemoryVT.

This fixes #89833.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
 llvm/test/CodeGen/RISCV/pr89833.ll          | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9c66f09a0cbc85..ce3eaf40bbd1ab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16832,7 +16832,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
           StrideC && StrideC->getZExtValue() == ElementSize)
         return DAG.getMaskedStore(Store->getChain(), DL, Value, Base,
                                   DAG.getUNDEF(XLenVT), Mask,
-                                  Store->getMemoryVT(), Store->getMemOperand(),
+                                  Value.getValueType(), Store->getMemOperand(),
                                   ISD::UNINDEXED, false);
       return SDValue();
     }
diff --git a/llvm/test/CodeGen/RISCV/pr89833.ll b/llvm/test/CodeGen/RISCV/pr89833.ll
index de3b5e27838623..54a985040e758a 100644
--- a/llvm/test/CodeGen/RISCV/pr89833.ll
+++ b/llvm/test/CodeGen/RISCV/pr89833.ll
@@ -6,8 +6,9 @@ declare void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8>,
 define void @test(<vscale x 16 x i16> %value, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT:    vse16.v v8, (zero), v0.t
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vnsrl.wi v12, v8, 0
+; CHECK-NEXT:    vse8.v v12, (zero), v0.t
 ; CHECK-NEXT:    ret
   %trunc = trunc <vscale x 16 x i16> %value to <vscale x 16 x i8>
   call void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8> %trunc, ptr null, i64 1, <vscale x 16 x i1> %mask)