[llvm] 7037878 - [RISCV][TableGen] Get right experimental extension name

[via llvm-commits]

Author: Pengcheng Wang
Date: 2024-04-28T11:16:43+08:00
New Revision: 7037878d2b4afbda436ec61008ac907bd782bdd8

URL: https://github.com/llvm/llvm-project/commit/7037878d2b4afbda436ec61008ac907bd782bdd8
DIFF: https://github.com/llvm/llvm-project/commit/7037878d2b4afbda436ec61008ac907bd782bdd8.diff

LOG: [RISCV][TableGen] Get right experimental extension name

We should remove the `experimental-` prefix when printing march
string.

We didn't meet this problem because there is no processor containing
experimental extensions.

Reviewers: fpetrogalli, asb, topperc

Reviewed By: topperc, asb

Pull Request: https://github.com/llvm/llvm-project/pull/90185

Added: 
    

Modified: 
    llvm/test/TableGen/riscv-target-def.td
    llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 01c72e07460e5e..865179fb79a6a7 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -83,6 +83,7 @@ def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
                                        FeatureStdExtI,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtZicsr,
+                                       FeatureStdExtZidummy,
                                        FeatureDummy]>;
 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
                                       NoSchedModel,
@@ -90,6 +91,7 @@ def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
                                        FeatureStdExtI,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtZicsr,
+                                       FeatureStdExtZidummy,
                                        FeatureDummy]>;
 def ROCKET : RISCVTuneProcessorModel<"rocket",
                                      NoSchedModel>;
@@ -125,8 +127,8 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
 
 // CHECK:      PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
 // CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
 
 // CHECK: #undef PROC
 

diff  --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 18c5be20244eff..787d22f635d00e 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -95,7 +95,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
 
   // Convert features to FeatureVector.
   for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
-    StringRef FeatureName = Feature->getValueAsString("Name");
+    StringRef FeatureName = getExtensionName(Feature);
     if (Feature->isSubClassOf("RISCVExtension")) {
       unsigned Major = Feature->getValueAsInt("MajorVersion");
       unsigned Minor = Feature->getValueAsInt("MinorVersion");