[llvm] [RISCV] Add Sched classes for vector crypto instructions (PR #90068)

[Craig Topper via llvm-commits]

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+//===- RISCVScheduleB.td - RISC-V Scheduling Definitions B -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+/// Define scheduler resources associated with def operands.
+
+/// Zvbb extension
+defm "" : LMULSchedWrites<"WriteVBREV">;
+defm "" : LMULSchedWrites<"WriteVCLZ">;
+defm "" : LMULSchedWrites<"WriteVCPOP">;
+defm "" : LMULSchedWrites<"WriteVCTZ">;
+defm "" : LMULSchedWrites<"WriteVWSLL">;
+
+/// Zvbc extension
+defm "" : LMULSchedWrites<"WriteVCLMUL">;
+defm "" : LMULSchedWrites<"WriteVCLMULH">;
+
+/// Zvkb extension
+defm "" : LMULSchedWrites<"WriteVANDN">;
+defm "" : LMULSchedWrites<"WriteVBREV8">;
+defm "" : LMULSchedWrites<"WriteVREV8">;
+defm "" : LMULSchedWrites<"WriteVROL">;
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topperc wrote:

I don't think we need separate VROL and VROR. But I do think we need RotateV, RotateX, and RotateI.

https://github.com/llvm/llvm-project/pull/90068