[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

[via llvm-commits]

Khao7342 wrote:

> Has the target architecture been finalized? (As in what it should be, not necessarily the rtl)
> 
> Just yesterday, there was a significant change in vector execution units:
> 
> [before](https://github.com/OpenXiangShan/XiangShan/blob/e25e4d90505c592524b410b127fe611ac49a3adf/src/main/scala/xiangshan/Parameters.scala#L355):
> 
> ```
> VFEX0: VfaluCfg, VfmaCfg, VialuCfg, VimacCfg
> VFEX1: VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg
> VFEX2: VfaluCfg, VfmaCfg, VialuCfg
> VFEX3: VfdivCfg, VidivCfg
> ```
> 
> [after](https://github.com/OpenXiangShan/XiangShan/blob/2e61107/src/main/scala/xiangshan/Parameters.scala#L357):
> 
> ```
> VFEX0: VfmaCfg, VialuCfg, VimacCfg, VppuCfg
> VFEX1: VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg
> VFEX2: VfmaCfg, VialuCfg, F2vCfg
> VFEX3: VfaluCfg, VfcvtCfg
> VFEX4: VfdivCfg, VidivCfg
> VFEX5: VfdivCfg, VidivCfg
> ```

Thanks for your attention to Xiangshan. KunMingHu's RTL has not been finalized yet. The development work on vectors is in the final stages of testing and performance optimization. And there won't be too many changes on the RTL.

https://github.com/llvm/llvm-project/pull/89359