[llvm] c793f4a - [RISCV] Add test coverage for mul (zext), 2^N + 2/4/8 [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-04-23T08:51:23-07:00
New Revision: c793f4a4dab058cee4f283100946a1bb8e465f59

URL: https://github.com/llvm/llvm-project/commit/c793f4a4dab058cee4f283100946a1bb8e465f59
DIFF: https://github.com/llvm/llvm-project/commit/c793f4a4dab058cee4f283100946a1bb8e465f59.diff

LOG: [RISCV] Add test coverage for mul (zext), 2^N + 2/4/8 [nfc]

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64zba.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index f31de84b8b047c..4eb493d642e853 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -753,6 +753,25 @@ define i64 @mul288(i64 %a) {
   ret i64 %c
 }
 
+define i64 @zext_mul68(i32 signext %a) {
+; RV64I-LABEL: zext_mul68:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 17
+; RV64I-NEXT:    slli a1, a1, 34
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    mulhu a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_mul68:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli.uw a1, a0, 6
+; RV64ZBA-NEXT:    sh2add.uw a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %b = zext i32 %a to i64
+  %c = mul i64 %b, 68
+  ret i64 %c
+}
+
 define i64 @zext_mul96(i32 signext %a) {
 ; RV64I-LABEL: zext_mul96:
 ; RV64I:       # %bb.0: