[llvm] [RISCV] Re-model RVV comparison instructions (PR #88868)

[Luke Lau via llvm-commits]

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@@ -88,11 +88,11 @@ define <vscale x 16 x i1> @nxv16i1(i1 %x, i1 %y) {
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vmv.v.x v8, a0
-; CHECK-NEXT:    vmsne.vi v10, v8, 0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
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lukel97 wrote:

For LMUL 8 the dest reg can only be v0,v8,v16,v24 now right? I think we would want to check that the register coalescer isn't propagating the VMM8 reg class to other uses. Or at least make sure that it gets inflated back to VR?

https://github.com/llvm/llvm-project/pull/88868