[llvm] aa1e912 - [InstCombine] Fix symbol conflicts in tests (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 21:43:11 PDT 2024
Author: Nikita Popov
Date: 2024-04-24T13:43:01+09:00
New Revision: aa1e912a1569d46a3b18c73367791a58a9c2b35d
URL: https://github.com/llvm/llvm-project/commit/aa1e912a1569d46a3b18c73367791a58a9c2b35d
DIFF: https://github.com/llvm/llvm-project/commit/aa1e912a1569d46a3b18c73367791a58a9c2b35d.diff
LOG: [InstCombine] Fix symbol conflicts in tests (NFC)
These tests break when regenerated due to symbol conflicts.
Added:
Modified:
llvm/test/Transforms/InstCombine/loadstore-alignment.ll
llvm/test/Transforms/InstCombine/memcpy-from-global.ll
llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/loadstore-alignment.ll b/llvm/test/Transforms/InstCombine/loadstore-alignment.ll
index 0fc82a1d534369..1027468d6715e8 100644
--- a/llvm/test/Transforms/InstCombine/loadstore-alignment.ll
+++ b/llvm/test/Transforms/InstCombine/loadstore-alignment.ll
@@ -9,24 +9,24 @@ target datalayout = "E-p:64:64:64-p1:64:64:64-p2:32:32:32-a0:0:8-f32:32:32-f64:6
define <2 x i64> @static_hem() {
; CHECK-LABEL: @static_hem(
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (<2 x i64>, ptr @x, i64 7), align 1
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr getelementptr (<2 x i64>, ptr @x, i64 7), align 1
+; CHECK-NEXT: ret <2 x i64> [[L]]
;
%t = getelementptr <2 x i64>, ptr @x, i32 7
- %tmp1 = load <2 x i64>, ptr %t, align 1
- ret <2 x i64> %tmp1
+ %l = load <2 x i64>, ptr %t, align 1
+ ret <2 x i64> %l
}
define <2 x i64> @hem(i32 %i) {
; CHECK-LABEL: @hem(
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I:%.*]] to i64
; CHECK-NEXT: [[T:%.*]] = getelementptr <2 x i64>, ptr @x, i64 [[TMP1]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1
+; CHECK-NEXT: ret <2 x i64> [[L]]
;
%t = getelementptr <2 x i64>, ptr @x, i32 %i
- %tmp1 = load <2 x i64>, ptr %t, align 1
- ret <2 x i64> %tmp1
+ %l = load <2 x i64>, ptr %t, align 1
+ ret <2 x i64> %l
}
define <2 x i64> @hem_2d(i32 %i, i32 %j) {
@@ -34,34 +34,34 @@ define <2 x i64> @hem_2d(i32 %i, i32 %j) {
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[J:%.*]] to i64
; CHECK-NEXT: [[T:%.*]] = getelementptr [13 x <2 x i64>], ptr @xx, i64 [[TMP1]], i64 [[TMP2]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1
+; CHECK-NEXT: ret <2 x i64> [[L]]
;
%t = getelementptr [13 x <2 x i64>], ptr @xx, i32 %i, i32 %j
- %tmp1 = load <2 x i64>, ptr %t, align 1
- ret <2 x i64> %tmp1
+ %l = load <2 x i64>, ptr %t, align 1
+ ret <2 x i64> %l
}
define <2 x i64> @foo() {
; CHECK-LABEL: @foo(
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @x, align 1
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr @x, align 1
+; CHECK-NEXT: ret <2 x i64> [[L]]
;
- %tmp1 = load <2 x i64>, ptr @x, align 1
- ret <2 x i64> %tmp1
+ %l = load <2 x i64>, ptr @x, align 1
+ ret <2 x i64> %l
}
define <2 x i64> @bar() {
; CHECK-LABEL: @bar(
; CHECK-NEXT: [[T:%.*]] = alloca <2 x i64>, align 16
; CHECK-NEXT: call void @kip(ptr nonnull [[T]])
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1
+; CHECK-NEXT: ret <2 x i64> [[L]]
;
%t = alloca <2 x i64>
call void @kip(ptr %t)
- %tmp1 = load <2 x i64>, ptr %t, align 1
- ret <2 x i64> %tmp1
+ %l = load <2 x i64>, ptr %t, align 1
+ ret <2 x i64> %l
}
define void @static_hem_store(<2 x i64> %y) {
diff --git a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll
index aeca0cd2924ea5..e9ff34735f1cf1 100644
--- a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll
+++ b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll
@@ -6,60 +6,60 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
define float @test1(i32 %hash, float %x, float %y, float %z, float %w) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[HASH:%.*]], 2
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], 124
-; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[TMP5]] to i64
-; CHECK-NEXT: [[TMP753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]]
-; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP753]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = fmul float [[TMP9]], [[X:%.*]]
-; CHECK-NEXT: [[TMP13:%.*]] = fadd float [[TMP11]], 0.000000e+00
-; CHECK-NEXT: [[TMP17_SUM52:%.*]] = or disjoint i32 [[TMP5]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TMP17_SUM52]] to i64
-; CHECK-NEXT: [[TMP1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]]
-; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP1851]], align 4
-; CHECK-NEXT: [[TMP21:%.*]] = fmul float [[TMP19]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP23:%.*]] = fadd float [[TMP21]], [[TMP13]]
-; CHECK-NEXT: [[TMP27_SUM50:%.*]] = or disjoint i32 [[TMP5]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP27_SUM50]] to i64
-; CHECK-NEXT: [[TMP2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]]
-; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP2849]], align 4
-; CHECK-NEXT: [[TMP31:%.*]] = fmul float [[TMP29]], [[Z:%.*]]
-; CHECK-NEXT: [[TMP33:%.*]] = fadd float [[TMP31]], [[TMP23]]
-; CHECK-NEXT: [[TMP37_SUM48:%.*]] = or disjoint i32 [[TMP5]], 3
-; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP37_SUM48]] to i64
-; CHECK-NEXT: [[TMP3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP3847]], align 4
-; CHECK-NEXT: [[TMP41:%.*]] = fmul float [[TMP39]], [[W:%.*]]
-; CHECK-NEXT: [[TMP43:%.*]] = fadd float [[TMP41]], [[TMP33]]
-; CHECK-NEXT: ret float [[TMP43]]
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[HASH:%.*]], 2
+; CHECK-NEXT: [[T5:%.*]] = and i32 [[T3]], 124
+; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[T5]] to i64
+; CHECK-NEXT: [[T753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]]
+; CHECK-NEXT: [[T9:%.*]] = load float, ptr [[T753]], align 4
+; CHECK-NEXT: [[T11:%.*]] = fmul float [[T9]], [[X:%.*]]
+; CHECK-NEXT: [[T13:%.*]] = fadd float [[T11]], 0.000000e+00
+; CHECK-NEXT: [[T17_SUM52:%.*]] = or disjoint i32 [[T5]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[T17_SUM52]] to i64
+; CHECK-NEXT: [[T1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]]
+; CHECK-NEXT: [[T19:%.*]] = load float, ptr [[T1851]], align 4
+; CHECK-NEXT: [[T21:%.*]] = fmul float [[T19]], [[Y:%.*]]
+; CHECK-NEXT: [[T23:%.*]] = fadd float [[T21]], [[T13]]
+; CHECK-NEXT: [[T27_SUM50:%.*]] = or disjoint i32 [[T5]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[T27_SUM50]] to i64
+; CHECK-NEXT: [[T2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]]
+; CHECK-NEXT: [[T29:%.*]] = load float, ptr [[T2849]], align 4
+; CHECK-NEXT: [[T31:%.*]] = fmul float [[T29]], [[Z:%.*]]
+; CHECK-NEXT: [[T33:%.*]] = fadd float [[T31]], [[T23]]
+; CHECK-NEXT: [[T37_SUM48:%.*]] = or disjoint i32 [[T5]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[T37_SUM48]] to i64
+; CHECK-NEXT: [[T3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]]
+; CHECK-NEXT: [[T39:%.*]] = load float, ptr [[T3847]], align 4
+; CHECK-NEXT: [[T41:%.*]] = fmul float [[T39]], [[W:%.*]]
+; CHECK-NEXT: [[T43:%.*]] = fadd float [[T41]], [[T33]]
+; CHECK-NEXT: ret float [[T43]]
;
entry:
- %lookupTable = alloca [128 x float], align 16 ; <ptr> [#uses=5]
+ %lookupTable = alloca [128 x float], align 16
call void @llvm.memcpy.p0.p0.i64(ptr align 16 %lookupTable, ptr align 16 @C.0.1248, i64 512, i1 false)
- %tmp3 = shl i32 %hash, 2 ; <i32> [#uses=1]
- %tmp5 = and i32 %tmp3, 124 ; <i32> [#uses=4]
- %tmp753 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp5 ; <ptr> [#uses=1]
- %tmp9 = load float, ptr %tmp753 ; <float> [#uses=1]
- %tmp11 = fmul float %tmp9, %x ; <float> [#uses=1]
- %tmp13 = fadd float %tmp11, 0.000000e+00 ; <float> [#uses=1]
- %tmp17.sum52 = or i32 %tmp5, 1 ; <i32> [#uses=1]
- %tmp1851 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp17.sum52 ; <ptr> [#uses=1]
- %tmp19 = load float, ptr %tmp1851 ; <float> [#uses=1]
- %tmp21 = fmul float %tmp19, %y ; <float> [#uses=1]
- %tmp23 = fadd float %tmp21, %tmp13 ; <float> [#uses=1]
- %tmp27.sum50 = or i32 %tmp5, 2 ; <i32> [#uses=1]
- %tmp2849 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp27.sum50 ; <ptr> [#uses=1]
- %tmp29 = load float, ptr %tmp2849 ; <float> [#uses=1]
- %tmp31 = fmul float %tmp29, %z ; <float> [#uses=1]
- %tmp33 = fadd float %tmp31, %tmp23 ; <float> [#uses=1]
- %tmp37.sum48 = or i32 %tmp5, 3 ; <i32> [#uses=1]
- %tmp3847 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp37.sum48 ; <ptr> [#uses=1]
- %tmp39 = load float, ptr %tmp3847 ; <float> [#uses=1]
- %tmp41 = fmul float %tmp39, %w ; <float> [#uses=1]
- %tmp43 = fadd float %tmp41, %tmp33 ; <float> [#uses=1]
- ret float %tmp43
+ %t3 = shl i32 %hash, 2
+ %t5 = and i32 %t3, 124
+ %t753 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t5
+ %t9 = load float, ptr %t753
+ %t11 = fmul float %t9, %x
+ %t13 = fadd float %t11, 0.000000e+00
+ %t17.sum52 = or i32 %t5, 1
+ %t1851 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t17.sum52
+ %t19 = load float, ptr %t1851
+ %t21 = fmul float %t19, %y
+ %t23 = fadd float %t21, %t13
+ %t27.sum50 = or i32 %t5, 2
+ %t2849 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t27.sum50
+ %t29 = load float, ptr %t2849
+ %t31 = fmul float %t29, %z
+ %t33 = fadd float %t31, %t23
+ %t37.sum48 = or i32 %t5, 3
+ %t3847 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t37.sum48
+ %t39 = load float, ptr %t3847
+ %t41 = fmul float %t39, %w
+ %t43 = fadd float %t41, %t33
+ ret float %t43
}
declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind
diff --git a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
index 866381ff2887f9..9c5bf3cb5a41bf 100644
--- a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
+++ b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
@@ -105,11 +105,11 @@ define i32 @
diff _types_
diff _width_no_merge(i1 %cond, i32 %a, i64 %b) {
; CHECK-LABEL: @
diff _types_
diff _width_no_merge(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
-; CHECK: A:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
; CHECK-NEXT: store i32 [[A:%.*]], ptr [[ALLOCA]], align 4
; CHECK-NEXT: br label [[SINK:%.*]]
-; CHECK: B:
+; CHECK: else:
; CHECK-NEXT: store i64 [[B:%.*]], ptr [[ALLOCA]], align 4
; CHECK-NEXT: br label [[SINK]]
; CHECK: sink:
@@ -118,11 +118,11 @@ define i32 @
diff _types_
diff _width_no_merge(i1 %cond, i32 %a, i64 %b) {
;
entry:
%alloca = alloca i64
- br i1 %cond, label %A, label %B
-A:
+ br i1 %cond, label %if, label %else
+if:
store i32 %a, ptr %alloca
br label %sink
-B:
+ else:
store i64 %b, ptr %alloca
br label %sink
sink:
@@ -134,11 +134,11 @@ define <4 x i32> @vec_no_merge(i1 %cond, <2 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @vec_no_merge(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
-; CHECK: A:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
; CHECK-NEXT: store <2 x i32> [[A:%.*]], ptr [[ALLOCA]], align 8
; CHECK-NEXT: br label [[SINK:%.*]]
-; CHECK: B:
+; CHECK: else:
; CHECK-NEXT: store <4 x i32> [[B:%.*]], ptr [[ALLOCA]], align 16
; CHECK-NEXT: br label [[SINK]]
; CHECK: sink:
@@ -147,11 +147,11 @@ define <4 x i32> @vec_no_merge(i1 %cond, <2 x i32> %a, <4 x i32> %b) {
;
entry:
%alloca = alloca i64
- br i1 %cond, label %A, label %B
-A:
+ br i1 %cond, label %if, label %else
+if:
store <2 x i32> %a, ptr %alloca
br label %sink
-B:
+else:
store <4 x i32> %b, ptr %alloca
br label %sink
sink:
@@ -195,11 +195,11 @@ define %struct.tup @multi_elem_struct_no_merge(i1 %cond, %struct.tup %a, half %b
; CHECK-LABEL: @multi_elem_struct_no_merge(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
-; CHECK: A:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
; CHECK-NEXT: store [[STRUCT_TUP:%.*]] [[A:%.*]], ptr [[ALLOCA]], align 4
; CHECK-NEXT: br label [[SINK:%.*]]
-; CHECK: B:
+; CHECK: else:
; CHECK-NEXT: store half [[B:%.*]], ptr [[ALLOCA]], align 2
; CHECK-NEXT: br label [[SINK]]
; CHECK: sink:
@@ -208,11 +208,11 @@ define %struct.tup @multi_elem_struct_no_merge(i1 %cond, %struct.tup %a, half %b
;
entry:
%alloca = alloca i64
- br i1 %cond, label %A, label %B
-A:
+ br i1 %cond, label %if, label %else
+if:
store %struct.tup %a, ptr %alloca
br label %sink
-B:
+else:
store half %b, ptr %alloca
br label %sink
sink:
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