[llvm] [AArch64][CodeGen] Add patterns for small negative VScale const (PR #89607)
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llvm-commits at lists.llvm.org
Tue Apr 23 05:38:40 PDT 2024
================
@@ -2583,6 +2583,27 @@ let Predicates = [HasSVEorSME] in {
sub_32)>;
}
+ // Add NoUseScalarIncVL to avoid affecting for patterns with UseScalarIncVL
+ let Predicates = [NoUseScalarIncVL] in {
+ def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+ (ADDXrs GPR64:$op, (RDVLI_XI $imm), 0)>;
----------------
vfdff wrote:
Yes, it is need. Without this, the case https://gcc.godbolt.org/z/TndasfP6h will transform into the following code because we matched the new added pattern `def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm_neg i32:$imm)))`
```
cnth x8, all, mul #2
sub x0, x0, w8
```
https://github.com/llvm/llvm-project/pull/89607
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