[llvm] [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add (PR #89532)

[via llvm-commits]

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@@ -510,6 +527,24 @@ define i32 @test25_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
   ret i32 %mul
 }
 
+; Negative: 35 = (((1<<4) + 1) << 1) + 1, the shift number 4 is out of bound
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vfdff wrote:

Update the tests with shift amount bound 4, thanks 

https://github.com/llvm/llvm-project/pull/89532