[llvm] [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add (PR #89532)
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Wed Apr 24 17:51:20 PDT 2024
https://github.com/vfdff updated https://github.com/llvm/llvm-project/pull/89532
>From a35d7d7d124172632a9a108f76deba647f4da863 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Wed, 24 Apr 2024 04:10:35 -0400
Subject: [PATCH 1/2] [AArch64][SelectionDAG] Correct the shift amounts bound
Accord D152827, when the shift amounts is 4 or less, they are
cheap as a move.
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++--
llvm/test/CodeGen/AArch64/mul_pow2.ll | 7 +++----
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 892b5853e00e14..3d2fa3953976b3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17610,8 +17610,8 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
APInt CVNMinus1 = CVN - 1;
unsigned ShiftM1 = CVMMinus1.logBase2();
unsigned ShiftN1 = CVNMinus1.logBase2();
- // LSLFast implicate that Shifts <= 3 places are fast
- if (ShiftM1 <= 3 && ShiftN1 <= 3) {
+ // ALULSLFast implicate that Shifts <= 4 places are fast
+ if (ShiftM1 <= 4 && ShiftN1 <= 4) {
SDValue MVal = Add(Shl(N0, ShiftM1), N0);
return Add(Shl(MVal, ShiftN1), MVal);
}
diff --git a/llvm/test/CodeGen/AArch64/mul_pow2.ll b/llvm/test/CodeGen/AArch64/mul_pow2.ll
index 90e560af4465a9..9f8ba8bc6bdc54 100644
--- a/llvm/test/CodeGen/AArch64/mul_pow2.ll
+++ b/llvm/test/CodeGen/AArch64/mul_pow2.ll
@@ -545,12 +545,11 @@ define i32 @test45(i32 %x) {
ret i32 %mul
}
-; Negative test: The shift amount 4 larger than 3
define i32 @test85_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-LABEL: test85_fast_shift:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #85 // =0x55
-; CHECK-NEXT: mul w0, w0, w8
+; CHECK-NEXT: add w8, w0, w0, lsl #2
+; CHECK-NEXT: add w0, w8, w8, lsl #4
; CHECK-NEXT: ret
;
; GISEL-LABEL: test85_fast_shift:
@@ -563,7 +562,7 @@ define i32 @test85_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
ret i32 %mul
}
-; Negative test: The shift amount 5 larger than 3
+; Negative test: The shift amount 5 larger than 4
define i32 @test297_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-LABEL: test297_fast_shift:
; CHECK: // %bb.0:
>From a6bdd6df23613c3ee5b3d7c31b1cf1fb78403a15 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Sun, 21 Apr 2024 01:22:13 -0400
Subject: [PATCH 2/2] [AArch64][SelectionDAG] Lower multiplication by a
constant to shl+add+shl+add
Change the costmodel to lower a = b * C where C = (1 + 2^m) * 2^n + 1 to
add w8, w0, w0, lsl #m
add w0, w0, w8, lsl #n
Note: The latency of add can vary depending on the shirt amount
They are cheap as a move when the shift amounts is 4 or less.
Fix part of https://github.com/llvm/llvm-project/issues/89430
---
.../Target/AArch64/AArch64ISelLowering.cpp | 35 +++++++++++-
llvm/test/CodeGen/AArch64/mul_pow2.ll | 57 ++++++++++++++++++-
2 files changed, 88 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 3d2fa3953976b3..223898e9d634d8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17585,12 +17585,32 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
return false;
};
+ // Can the const C be decomposed into (2^M + 1) * 2^N + 1), eg:
+ // C = 11 is equal to (1+4)*2+1, we don't decompose it into (1+2)*4-1 as
+ // the (2^N - 1) can't be execused via a single instruction.
+ auto isPowPlusPlusOneConst = [](APInt C, APInt &M, APInt &N) {
+ APInt CVMinus1 = C - 1;
+ if (CVMinus1.isNegative())
+ return false;
+ unsigned TrailingZeroes = CVMinus1.countr_zero();
+ APInt SCVMinus1 = CVMinus1.ashr(TrailingZeroes) - 1;
+ if (SCVMinus1.isPowerOf2()) {
+ unsigned BitWidth = SCVMinus1.getBitWidth();
+ M = APInt(BitWidth, SCVMinus1.logBase2());
+ N = APInt(BitWidth, TrailingZeroes);
+ return true;
+ }
+ return false;
+ };
+
if (ConstValue.isNonNegative()) {
// (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
// (mul x, 2^N - 1) => (sub (shl x, N), x)
// (mul x, (2^(N-M) - 1) * 2^M) => (sub (shl x, N), (shl x, M))
// (mul x, (2^M + 1) * (2^N + 1))
// => MV = (add (shl x, M), x); (add (shl MV, N), MV)
+ // (mul x, (2^M + 1) * 2^N + 1))
+ // => MV = add (shl x, M), x); add (shl MV, N), x)
APInt SCVMinus1 = ShiftedConstValue - 1;
APInt SCVPlus1 = ShiftedConstValue + 1;
APInt CVPlus1 = ConstValue + 1;
@@ -17604,8 +17624,9 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
} else if (SCVPlus1.isPowerOf2()) {
ShiftAmt = SCVPlus1.logBase2() + TrailingZeroes;
return Sub(Shl(N0, ShiftAmt), Shl(N0, TrailingZeroes));
- } else if (Subtarget->hasALULSLFast() &&
- isPowPlusPlusConst(ConstValue, CVM, CVN)) {
+ }
+ if (Subtarget->hasALULSLFast() &&
+ isPowPlusPlusConst(ConstValue, CVM, CVN)) {
APInt CVMMinus1 = CVM - 1;
APInt CVNMinus1 = CVN - 1;
unsigned ShiftM1 = CVMMinus1.logBase2();
@@ -17616,6 +17637,16 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
return Add(Shl(MVal, ShiftN1), MVal);
}
}
+ if (Subtarget->hasALULSLFast() &&
+ isPowPlusPlusOneConst(ConstValue, CVM, CVN)) {
+ unsigned ShiftM = CVM.getZExtValue();
+ unsigned ShiftN = CVN.getZExtValue();
+ // ALULSLFast implicate that Shifts <= 4 places are fast
+ if (ShiftM <= 4 && ShiftN <= 4) {
+ SDValue MVal = Add(Shl(N0, CVM.getZExtValue()), N0);
+ return Add(Shl(MVal, CVN.getZExtValue()), N0);
+ }
+ }
} else {
// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
// (mul x, -(2^N + 1)) => - (add (shl x, N), x)
diff --git a/llvm/test/CodeGen/AArch64/mul_pow2.ll b/llvm/test/CodeGen/AArch64/mul_pow2.ll
index 9f8ba8bc6bdc54..0c9ea51ba367e9 100644
--- a/llvm/test/CodeGen/AArch64/mul_pow2.ll
+++ b/llvm/test/CodeGen/AArch64/mul_pow2.ll
@@ -410,6 +410,23 @@ define i32 @test11(i32 %x) {
ret i32 %mul
}
+define i32 @test11_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
+; CHECK-LABEL: test11_fast_shift:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add w8, w0, w0, lsl #2
+; CHECK-NEXT: add w0, w0, w8, lsl #1
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: test11_fast_shift:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #11 // =0xb
+; GISEL-NEXT: mul w0, w0, w8
+; GISEL-NEXT: ret
+
+ %mul = mul nsw i32 %x, 11 ; 11 = (((1<<2) + 1) << 1) + 1
+ ret i32 %mul
+}
+
define i32 @test12(i32 %x) {
; CHECK-LABEL: test12:
; CHECK: // %bb.0:
@@ -545,6 +562,24 @@ define i32 @test45(i32 %x) {
ret i32 %mul
}
+; Negative test: The shift number 5 is out of bound
+define i32 @test67_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
+; CHECK-LABEL: test67_fast_shift:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #67 // =0x43
+; CHECK-NEXT: mul w0, w0, w8
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: test67_fast_shift:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #67 // =0x43
+; GISEL-NEXT: mul w0, w0, w8
+; GISEL-NEXT: ret
+
+ %mul = mul nsw i32 %x, 67 ; 67 = (((1<<5) + 1) << 1) + 1
+ ret i32 %mul
+}
+
define i32 @test85_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-LABEL: test85_fast_shift:
; CHECK: // %bb.0:
@@ -562,6 +597,24 @@ define i32 @test85_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
ret i32 %mul
}
+; Negative test: The shift number 5 is out of bound
+define i32 @test97_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
+; CHECK-LABEL: test97_fast_shift:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #97 // =0x61
+; CHECK-NEXT: mul w0, w0, w8
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: test97_fast_shift:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #97 // =0x61
+; GISEL-NEXT: mul w0, w0, w8
+; GISEL-NEXT: ret
+
+ %mul = mul nsw i32 %x, 97 ; 97 = ((2 + 1) << 5) + 1
+ ret i32 %mul
+}
+
; Negative test: The shift amount 5 larger than 4
define i32 @test297_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-LABEL: test297_fast_shift:
@@ -857,9 +910,9 @@ define <4 x i32> @muladd_demand_commute(<4 x i32> %x, <4 x i32> %y) {
;
; GISEL-LABEL: muladd_demand_commute:
; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI49_0
+; GISEL-NEXT: adrp x8, .LCPI52_0
; GISEL-NEXT: movi v3.4s, #1, msl #16
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI49_0]
+; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI52_0]
; GISEL-NEXT: mla v1.4s, v0.4s, v2.4s
; GISEL-NEXT: and v0.16b, v1.16b, v3.16b
; GISEL-NEXT: ret
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