[llvm] [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions (PR #89976)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 12:08:52 PDT 2024
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/89976
Inspired by https://github.com/llvm/llvm-project/pull/89966, this patch handles the special case `binop_allwusers<and> GPR:$rs1, 0xffffffff -> copy $rs1` to avoid creating redundant `andi rd, rs1, -1` instructions.
>From d78c9d699a0363c1819dfc2c86c99871ffa069ee Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 25 Apr 2024 02:45:22 +0800
Subject: [PATCH 1/2] [RISCV][ISel] Add pre-commit tests. NFC.
---
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index 6a441e2b9f67fb..3e37d17ebfcae4 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -192,3 +192,18 @@ entry:
%or = or i32 %and, 255
ret i32 %or
}
+
+define i64 @and_allones(i32 signext %x) {
+; CHECK-LABEL: and_allones:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi a0, a0, -1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: sll a0, a1, a0
+; CHECK-NEXT: ret
+entry:
+ %y = zext i32 %x to i64
+ %shamt = add nsw i64 %y, -1
+ %ret = shl i64 1, %shamt
+ ret i64 %ret
+}
>From 23cec6133e7ca5b31d179064f4ae81522a5abd00 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 25 Apr 2024 02:48:27 +0800
Subject: [PATCH 2/2] [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +
.../CodeGen/RISCV/rv64-legal-i32/rv64zba.ll | 3 -
.../RISCV/rv64-legal-i32/rv64zbb-zbkb.ll | 58 ++---
.../test/CodeGen/RISCV/rv64i-demanded-bits.ll | 1 -
llvm/test/CodeGen/RISCV/rv64zba.ll | 3 -
.../rvv/fixed-vectors-reduction-int-vp.ll | 104 +++-----
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 230 ++++++------------
llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll | 1 -
8 files changed, 132 insertions(+), 270 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index f9dadc6c0d4895..da4020758eb6e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1813,6 +1813,8 @@ def : Pat<(binop_allwusers<srl> (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
// Use binop_allwusers to recover immediates that may have been broken by
// SimplifyDemandedBits.
+def : Pat<(binop_allwusers<and> GPR:$rs1, 0xffffffff),
+ (COPY GPR:$rs1)>;
def : Pat<(binop_allwusers<and> GPR:$rs1, u32simm12:$imm),
(ANDI GPR:$rs1, u32simm12:$imm)>;
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
index 9f06a9dd124cef..ff6d3630c21152 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
@@ -647,7 +647,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul12884901888:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
@@ -670,7 +669,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul21474836480:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
@@ -693,7 +691,6 @@ define i64 @zext_mul38654705664(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul38654705664:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
index 39a5b9b0f3676c..c98ad4592a6620 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
@@ -102,11 +102,10 @@ declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: rol_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a2, a1, -1
-; RV64I-NEXT: sllw a1, a0, a1
-; RV64I-NEXT: negw a2, a2
-; RV64I-NEXT: srlw a0, a0, a2
-; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: sllw a2, a0, a1
+; RV64I-NEXT: negw a1, a1
+; RV64I-NEXT: srlw a0, a0, a1
+; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: rol_i32:
@@ -121,11 +120,10 @@ define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: rol_i32_nosext:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a3, a1, -1
-; RV64I-NEXT: sllw a1, a0, a1
-; RV64I-NEXT: negw a3, a3
-; RV64I-NEXT: srlw a0, a0, a3
-; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: sllw a3, a0, a1
+; RV64I-NEXT: negw a1, a1
+; RV64I-NEXT: srlw a0, a0, a1
+; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
@@ -142,12 +140,11 @@ define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: rol_i32_neg_constant_rhs:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a1, a0, -1
-; RV64I-NEXT: li a2, -2
-; RV64I-NEXT: sllw a0, a2, a0
-; RV64I-NEXT: negw a1, a1
-; RV64I-NEXT: srlw a1, a2, a1
-; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: li a1, -2
+; RV64I-NEXT: sllw a2, a1, a0
+; RV64I-NEXT: negw a0, a0
+; RV64I-NEXT: srlw a0, a1, a0
+; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: rol_i32_neg_constant_rhs:
@@ -183,11 +180,10 @@ declare i32 @llvm.fshr.i32(i32, i32, i32)
define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: ror_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a2, a1, -1
-; RV64I-NEXT: srlw a1, a0, a1
-; RV64I-NEXT: negw a2, a2
-; RV64I-NEXT: sllw a0, a0, a2
-; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srlw a2, a0, a1
+; RV64I-NEXT: negw a1, a1
+; RV64I-NEXT: sllw a0, a0, a1
+; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: ror_i32:
@@ -202,11 +198,10 @@ define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: ror_i32_nosext:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a3, a1, -1
-; RV64I-NEXT: srlw a1, a0, a1
-; RV64I-NEXT: negw a3, a3
-; RV64I-NEXT: sllw a0, a0, a3
-; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srlw a3, a0, a1
+; RV64I-NEXT: negw a1, a1
+; RV64I-NEXT: sllw a0, a0, a1
+; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
@@ -223,12 +218,11 @@ define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: ror_i32_neg_constant_rhs:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a1, a0, -1
-; RV64I-NEXT: li a2, -2
-; RV64I-NEXT: srlw a0, a2, a0
-; RV64I-NEXT: negw a1, a1
-; RV64I-NEXT: sllw a1, a2, a1
-; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: li a1, -2
+; RV64I-NEXT: srlw a2, a1, a0
+; RV64I-NEXT: negw a0, a0
+; RV64I-NEXT: sllw a0, a1, a0
+; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: ror_i32_neg_constant_rhs:
diff --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index 3e37d17ebfcae4..b8c43289bdfed2 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -196,7 +196,6 @@ entry:
define i64 @and_allones(i32 signext %x) {
; CHECK-LABEL: and_allones:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andi a0, a0, -1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sll a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 0efc45b99289a7..6446c11955d882 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -864,7 +864,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul12884901888:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
@@ -887,7 +886,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul21474836480:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
@@ -910,7 +908,6 @@ define i64 @zext_mul38654705664(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul38654705664:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 2495178ea762d9..02a989a9699606 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -574,24 +574,14 @@ define signext i32 @vpreduce_add_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m
declare i32 @llvm.vp.reduce.umax.v2i32(i32, <2 x i32>, <2 x i1>, i32)
define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v2i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v2i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -614,24 +604,14 @@ define signext i32 @vpreduce_smax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
declare i32 @llvm.vp.reduce.umin.v2i32(i32, <2 x i32>, <2 x i1>, i32)
define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umin_v2i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umin_v2i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umin_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -714,24 +694,14 @@ define signext i32 @vpreduce_add_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m
declare i32 @llvm.vp.reduce.umax.v4i32(i32, <4 x i32>, <4 x i1>, i32)
define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v4i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v4i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -754,24 +724,14 @@ define signext i32 @vpreduce_smax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
declare i32 @llvm.vp.reduce.umin.v4i32(i32, <4 x i32>, <4 x i1>, i32)
define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umin_v4i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umin_v4i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umin_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 618e169e1f9654..7bcf37b1af3c8f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -841,24 +841,14 @@ define signext i32 @vpreduce_add_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
declare i32 @llvm.vp.reduce.umax.nxv1i32(i32, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv1i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv1i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -881,24 +871,14 @@ define signext i32 @vpreduce_smax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
declare i32 @llvm.vp.reduce.umin.nxv1i32(i32, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umin_nxv1i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umin_nxv1i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umin_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -981,24 +961,14 @@ define signext i32 @vpreduce_add_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
declare i32 @llvm.vp.reduce.umax.nxv2i32(i32, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv2i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv2i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -1021,24 +991,14 @@ define signext i32 @vpreduce_smax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
declare i32 @llvm.vp.reduce.umin.nxv2i32(i32, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umin_nxv2i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v9, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV32-NEXT: vmv.x.s a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umin_nxv2i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v9, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
-; RV64-NEXT: vmv.x.s a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umin_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -1121,24 +1081,14 @@ define signext i32 @vpreduce_add_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
declare i32 @llvm.vp.reduce.umax.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv4i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v10, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
-; RV32-NEXT: vmv.x.s a0, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv4i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v10, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t
-; RV64-NEXT: vmv.x.s a0, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -1146,56 +1096,30 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
declare i32 @llvm.vp.reduce.umax.nxv32i32(i32, <vscale x 32 x i32>, <vscale x 32 x i1>, i32)
define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv32i32:
-; RV32: # %bb.0:
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: srli a2, a3, 2
-; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vx v24, v0, a2
-; RV32-NEXT: slli a3, a3, 1
-; RV32-NEXT: sub a2, a1, a3
-; RV32-NEXT: sltu a4, a1, a2
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a2, a4, a2
-; RV32-NEXT: bltu a1, a3, .LBB67_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB67_2:
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vredmaxu.vs v25, v16, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv32i32:
-; RV64: # %bb.0:
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: srli a2, a3, 2
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v24, v0, a2
-; RV64-NEXT: andi a2, a0, -1
-; RV64-NEXT: slli a3, a3, 1
-; RV64-NEXT: sub a0, a1, a3
-; RV64-NEXT: sltu a4, a1, a0
-; RV64-NEXT: addi a4, a4, -1
-; RV64-NEXT: and a0, a4, a0
-; RV64-NEXT: bltu a1, a3, .LBB67_2
-; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a1, a3
-; RV64-NEXT: .LBB67_2:
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vmv.s.x v25, a2
-; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v24
-; RV64-NEXT: vredmaxu.vs v25, v16, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umax_nxv32i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a2, a3, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v24, v0, a2
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: sub a2, a1, a3
+; CHECK-NEXT: sltu a4, a1, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: bltu a1, a3, .LBB67_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB67_2:
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vredmaxu.vs v25, v16, v25, v0.t
+; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv32i32(i32 %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i32 %r
}
@@ -1218,24 +1142,14 @@ define signext i32 @vpreduce_smax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
declare i32 @llvm.vp.reduce.umin.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umin_nxv4i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vmv.s.x v10, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
-; RV32-NEXT: vmv.x.s a0, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umin_nxv4i32:
-; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vmv.s.x v10, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t
-; RV64-NEXT: vmv.x.s a0, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: vpreduce_umin_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vredminu.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
+; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
index 21ddf1a6e114d4..d70f619c3601a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
@@ -1484,7 +1484,6 @@ define <vscale x 8 x i64> @vwadd_vx_splat_zext(<vscale x 8 x i32> %va, i32 %b) {
;
; RV64-LABEL: vwadd_vx_splat_zext:
; RV64: # %bb.0:
-; RV64-NEXT: andi a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; RV64-NEXT: vwaddu.vx v16, v8, a0
; RV64-NEXT: vmv8r.v v8, v16
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