[llvm] [RISCV][MCP] Remove redundant move from tail duplication (PR #89865)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 23:01:54 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/89865
>From f79afd508e775733ae2e9f66b63c81a0254c06de Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 23 Apr 2024 19:54:44 -0700
Subject: [PATCH 1/3] [RISCV] precommit for redundant copy
---
.../redundant-copy-from-tail-duplicate.ll | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
diff --git a/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll b/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
new file mode 100644
index 00000000000000..0e0792b514e534
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=riscv64 -mcpu=sifive-x280 -O3 | FileCheck %s
+
+
+define signext i32 @sum(ptr %a, i32 signext %n, i1 %prof.min.iters.check, <vscale x 8 x i1> %0, <vscale x 8 x i1> %1) {
+; CHECK-LABEL: sum:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi a2, a2, 1
+; CHECK-NEXT: beqz a2, .LBB0_4
+; CHECK-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: .LBB0_2: # %for.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: lw a3, 0(a0)
+; CHECK-NEXT: addi a0, a0, 4
+; CHECK-NEXT: bnez a1, .LBB0_2
+; CHECK-NEXT: # %bb.3: # %for.end
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_4: # %vector.ph
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v12, zero
+; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma
+; CHECK-NEXT: vredsum.vs v8, v8, v12, v0.t
+; CHECK-NEXT: vmv.x.s a2, v8
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+entry:
+ br i1 %prof.min.iters.check, label %for.body, label %vector.ph
+
+vector.ph: ; preds = %entry
+ %2 = tail call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i1> %0, i32 1)
+ br label %for.end
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+ %red.05 = phi i32 [ %3, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr i32, ptr %a, i64 %indvars.iv
+ %3 = load i32, ptr %arrayidx, align 4
+ %indvars.iv.next = add i64 %indvars.iv, 1
+ %exitcond.not = icmp eq i32 %n, 0
+ br i1 %exitcond.not, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %vector.ph
+ %red.0.lcssa = phi i32 [ %2, %vector.ph ], [ %red.05, %for.body ]
+ ret i32 %red.0.lcssa
+}
+
+declare i32 @llvm.vp.reduce.add.nxv8i32(i32, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
>From 914edfc28ab9e55038c3d9688903d157afd16945 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 23 Apr 2024 20:10:51 -0700
Subject: [PATCH 2/3] [RISCV] Remove redundant move from tail duplication
Tail duplication will generate the redundant move before return. It is because the MachineCopyPropogation can't recognize COPY after post-RA pseudoExpand.
This patch
1. Keep renamable after post-RA pseudoExpand
2. Let MachineCopyPropogation recognize `%0 = ADDI %1, 0` as COPY
---
llvm/lib/CodeGen/MachineCopyPropagation.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +++++---
.../CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll | 3 +--
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 8dc6781fcb018f..5aaf6b31dcc542 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -1053,7 +1053,7 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
// Ignore non-trivial COPYs.
std::optional<DestSourcePair> CopyOperands =
isCopyInstr(MI, *TII, UseCopyInstr);
- if (CopyOperands && MI.getNumOperands() == 2) {
+ if (CopyOperands) {
Register DefReg = CopyOperands->Destination->getReg();
Register SrcReg = CopyOperands->Source->getReg();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 70ac1f8a592e02..c05bf8b0f68e08 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -424,9 +424,11 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addImm(0);
+ auto MI = BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addImm(0);
+ MI->getOperand(0).setIsRenamable(MBBI->getOperand(0).isRenamable());
+ MI->getOperand(1).setIsRenamable(MBBI->getOperand(1).isRenamable());
return;
}
diff --git a/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll b/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
index 0e0792b514e534..d00e10dbd9c7f3 100644
--- a/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
+++ b/llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
@@ -24,8 +24,7 @@ define signext i32 @sum(ptr %a, i32 signext %n, i1 %prof.min.iters.check, <vscal
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; CHECK-NEXT: vredsum.vs v8, v8, v12, v0.t
-; CHECK-NEXT: vmv.x.s a2, v8
-; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
br i1 %prof.min.iters.check, label %for.body, label %vector.ph
>From 9c0982b338a2bfb1b716002013dbb2b26a2c36c8 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 23 Apr 2024 22:56:21 -0700
Subject: [PATCH 3/3] Remove copyPhysReg change and remove IsRenamable checking
---
llvm/lib/CodeGen/MachineCopyPropagation.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 5aaf6b31dcc542..75a636c4ed8eb9 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -983,7 +983,7 @@ static bool isBackwardPropagatableCopy(const DestSourcePair &CopyOperands,
if (MRI.isReserved(Def) || MRI.isReserved(Src))
return false;
- return CopyOperands.Source->isRenamable() && CopyOperands.Source->isKill();
+ return CopyOperands.Source->isKill();
}
void MachineCopyPropagation::propagateDefs(MachineInstr &MI) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index c05bf8b0f68e08..70ac1f8a592e02 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -424,11 +424,9 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
- auto MI = BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addImm(0);
- MI->getOperand(0).setIsRenamable(MBBI->getOperand(0).isRenamable());
- MI->getOperand(1).setIsRenamable(MBBI->getOperand(1).isRenamable());
+ BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addImm(0);
return;
}
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