[llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)

[Yeting Kuo via llvm-commits]

yetingk wrote:

> Mask load/store. Their SEW are always 1.

Could we make `VSEW` also support SEW=1 scenario?

https://github.com/llvm/llvm-project/pull/90396