[llvm] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (PR #90208)

[Yingwei Zheng via llvm-commits]

================
@@ -7503,6 +7503,17 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
       return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal);
     }
 
+    // c = setcc f, 0, seteq
+    // (select c, t, f) -> (or f, (czero_nez t, f))
----------------
dtcxzyw wrote:

Yeah, it would be better to handle general cases :)
Can you try the following diff?

```
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 539aa3525545..1960e7917080 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16179,6 +16179,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                            N->getOperand(0), Cond);
       }
     }
+    // czero_eqz x, (setcc x, 0, ne) -> x
+    // czero_nez x, (setcc x, 0, eq) -> x
+    if (N->getOperand(1).getOpcode() == ISD::SETCC && isNullConstant(N->getOperand(1).getOperand(1)) &&
+      cast<CondCodeSDNode>(N->getOperand(1).getOperand(2))->get() == (N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE : ISD::CondCode::SETEQ)
+      && N->getOperand(0) == N->getOperand(1).getOperand(0))
+      return N->getOperand(0);
     return SDValue();
 
   case RISCVISD::SELECT_CC: {
```

https://github.com/llvm/llvm-project/pull/90208