[llvm] [DAGCombiner] Fix miscompile bug in combineShiftOfShiftedLogic (PR #89616)

[Björn Pettersson via llvm-commits]

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@@ -787,3 +787,38 @@ define <4 x i32> @or_tree_with_mismatching_shifts_vec_i32(<4 x i32> %a, <4 x i32
   %r = or <4 x i32> %or.ab, %or.cd
   ret <4 x i32> %r
 }
+
+; FIXME: Reproducer for a DAGCombiner::combineShiftOfShiftedLogic
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bjope wrote:

Thanks!   (I actually realized that I had forgotten to remove this when I woke up this morning, but was not quick enough to fix it before you found it.)

https://github.com/llvm/llvm-project/pull/89616