[llvm] 37e27a4 - [llvm-exegesis] Add support for alderlake (#88967)
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Tue Apr 23 10:42:59 PDT 2024
Author: Aiden Grossman
Date: 2024-04-23T10:42:56-07:00
New Revision: 37e27a4d6509fa6432d0125bf43249d2ad01dbc3
URL: https://github.com/llvm/llvm-project/commit/37e27a4d6509fa6432d0125bf43249d2ad01dbc3
DIFF: https://github.com/llvm/llvm-project/commit/37e27a4d6509fa6432d0125bf43249d2ad01dbc3.diff
LOG: [llvm-exegesis] Add support for alderlake (#88967)
This patch adds the PFM counter definitions for Intel alderlake CPUs.
Added:
Modified:
llvm/lib/Target/X86/X86PfmCounters.td
llvm/lib/Target/X86/X86SchedAlderlakeP.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td
index d87a559aa353b1..2b1dac411c9927 100644
--- a/llvm/lib/Target/X86/X86PfmCounters.td
+++ b/llvm/lib/Target/X86/X86PfmCounters.td
@@ -204,6 +204,22 @@ def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
+def AlderLakePfmCounters : ProcPfmCounters {
+ let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+ let UopsCounter = UopsIssuedPfmCounter;
+ let IssueCounters = [
+ PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">,
+ PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">,
+ PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched_port:port_2_3_10">,
+ PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">,
+ PfmIssueCounter<"ADLPPort05_11", "uops_dispatched_port:port_5_11">,
+ PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">,
+ PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8">
+ ];
+ let ValidationCounters = DefaultIntelPfmValidationCounters;
+}
+def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;
+
// AMD X86 Counters.
defvar DefaultAMDPfmValidationCounters = [
PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 6f9d2cf7ffdf47..7756cd57cf7f84 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -60,6 +60,8 @@ def ADLPPort01_05_10 : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>;
def ADLPPort02_03 : ProcResGroup<[ADLPPort02, ADLPPort03]>;
def ADLPPort02_03_07 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>;
def ADLPPort02_03_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort11]>;
+def ADLPPort02_03_10 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort10]>;
+def ADLPPort05_11 : ProcResGroup<[ADLPPort05, ADLPPort11]>;
def ADLPPort07_08 : ProcResGroup<[ADLPPort07, ADLPPort08]>;
// EU has 112 reservation stations.
@@ -79,6 +81,10 @@ def ADLPPort02_03_07_08_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07,
let BufferSize = 72;
}
+def ADLPPortAny : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort02, ADLPPort03,
+ ADLPPort04, ADLPPort05, ADLPPort06, ADLPPort07,
+ ADLPPort08, ADLPPort09, ADLPPort10, ADLPPort11]>;
+
// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
// until 5 cycles after the memory operand.
def : ReadAdvance<ReadAfterLd, 5>;
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