[llvm] [RISCV] Support instruction sizes up to 176-bits in disassembler. (PR #90371)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 28 21:11:07 PDT 2024
================
@@ -656,12 +656,44 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
- // TODO: This will need modification when supporting instruction set
- // extensions with instructions > 32-bits (up to 176 bits wide).
+ // It's a 16 bit instruction if bit 0 and 1 are not 0x3.
----------------
wangpc-pp wrote:
```suggestion
// It's a 16 bit instruction if bit 0 and 1 are not 0b11.
```
https://github.com/llvm/llvm-project/pull/90371
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