[llvm] [AArch64] Optimization of repeated constant loads (#51483) (PR #86249)
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Mon Apr 22 10:48:32 PDT 2024
https://github.com/ParkHanbum updated https://github.com/llvm/llvm-project/pull/86249
>From 16bb2538c1cc77053db4eb544e342216e35ec67e Mon Sep 17 00:00:00 2001
From: Hanbum Park <kese111 at gmail.com>
Date: Sun, 21 Apr 2024 18:41:21 +0900
Subject: [PATCH 1/2] [AArch64] Add PreTest for optimizing `MOV` to `ORR`
---
.../CodeGen/AArch64/movimm-expand-ldst.mir | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
diff --git a/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir b/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
new file mode 100644
index 00000000000000..de14437108c93f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=aarch64 -verify-machineinstrs -run-pass=aarch64-expand-pseudo -run-pass=aarch64-ldst-opt -debug-only=aarch64-ldst-opt %s -o - | FileCheck %s
+---
+name: test_fold_repeating_constant_load
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_fold_repeating_constant_load
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x0 = MOVZXi 49370, 0
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 16
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 32
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 48
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
+ renamable $x0 = MOVi64imm 90284035103834330
+ RET_ReallyLR implicit $x0
+...
+---
+name: test_fold_repeating_constant_load_neg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_fold_repeating_constant_load_neg
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x0 = MOVZXi 320, 0
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 16
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 32
+ ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 48
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
+ renamable $x0 = MOVi64imm -4550323095879417536
+ RET_ReallyLR implicit $x0
>From 1d03a1b0648a9e5b0cce6d7ddf6296edf1ac9b8e Mon Sep 17 00:00:00 2001
From: Hanbum Park <kese111 at gmail.com>
Date: Fri, 12 Apr 2024 16:53:37 +0900
Subject: [PATCH 2/2] [AArch64] Optimize `MOV` to `ORR` when load symmetric
constants (#51483)
This change looks for cases of symmetric constant loading.
`symmetric constant load` is when the upper 32 bits and lower 32 bits
of a 64-bit register load the same value.
When it finds this, it replaces it with an instruction that loads only
the lower 32 bits of the constant and stores it in the upper and lower
bits simultaneously.
For example:
renamable $x8 = MOVZXi 49370, 0
renamable $x8 = MOVKXi $x8, 320, 16
renamable $x8 = MOVKXi $x8, 49370, 32
renamable $x8 = MOVKXi $x8, 320, 48
becomes
renamable $x8 = MOVZXi 49370, 0
renamable $x8 = MOVKXi $x8, 320, 16
renamable $x8 = ORRXrs $x8, $x8, 32
---
llvm/lib/Target/AArch64/AArch64ExpandImm.cpp | 10 ++++++++++
.../lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 13 +++++++++++++
llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir | 6 ++----
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
index a7d72b59b1d5a6..2d37d232b8edd9 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
@@ -509,6 +509,16 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
Imm = ~Imm;
unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
+ Shift += 16;
+ Imm16 = (Imm >> Shift) & Mask;
+ if (Imm16 != (isNeg ? Mask : 0))
+ Insn.push_back(
+ {Opc, Imm16, AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)});
+ if (Imm != 0 && (Imm >> 32) == (Imm & UINT_MAX)) {
+ Insn.push_back({BitSize == 32 ? AArch64::ORRWrs : AArch64::ORRXrs, 0, 32});
+ return;
+ }
+
while (Shift < LastShift) {
Shift += 16;
Imm16 = (Imm >> Shift) & Mask;
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 03f0778bae59d5..36957bb0f5a059 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -168,6 +168,19 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
.addImm(I->Op2));
}
break;
+ case AArch64::ORRWrs:
+ case AArch64::ORRXrs: {
+ Register DstReg = MI.getOperand(0).getReg();
+ bool DstIsDead = MI.getOperand(0).isDead();
+ MIBS.push_back(
+ BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
+ .addReg(DstReg, RegState::Define |
+ getDeadRegState(DstIsDead && LastItem) |
+ RenamableState)
+ .addReg(DstReg)
+ .addReg(DstReg)
+ .addImm(I->Op2));
+ } break;
case AArch64::ANDXri:
case AArch64::EORXri:
if (I->Op1 == 0) {
diff --git a/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir b/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
index de14437108c93f..1ec2a00f67690b 100644
--- a/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
+++ b/llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
@@ -11,8 +11,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x0 = MOVZXi 49370, 0
; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 16
- ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 32
- ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 48
+ ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 32
; CHECK-NEXT: RET undef $lr, implicit $x0
renamable $x0 = MOVi64imm 90284035103834330
RET_ReallyLR implicit $x0
@@ -28,8 +27,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x0 = MOVZXi 320, 0
; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 16
- ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 32
- ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 48
+ ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 32
; CHECK-NEXT: RET undef $lr, implicit $x0
renamable $x0 = MOVi64imm -4550323095879417536
RET_ReallyLR implicit $x0
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