[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[Michael Maitland via llvm-commits]

================
@@ -166,6 +166,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
   BitVector ImplUseRegs = RATC.emptyRegisters();
   BitVector AllDefRegs = RATC.emptyRegisters();
   BitVector AllUseRegs = RATC.emptyRegisters();
+  BitVector MemoryRegs = RATC.emptyRegisters();
----------------
michaelmaitland wrote:

It seems that `MemoryRegs` is not used. Do we need it?

https://github.com/llvm/llvm-project/pull/89047