[llvm] [RISCV] Codegen support for XCVbi extension (PR #89719)

[Craig Topper via llvm-commits]

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@@ -17656,7 +17656,9 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   // is checked here and handled by a separate function -
   // EmitLoweredCascadedSelect.
   Register LHS = MI.getOperand(1).getReg();
-  Register RHS = MI.getOperand(2).getReg();
+  Register RHS;
+  if (MI.getOperand(2).isReg())
+    RHS = MI.getOperand(2).getReg();
   auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
 
   SmallVector<MachineInstr *, 4> SelectDebugValues;
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topperc wrote:

I think you need to add `MI.getOpcode() != RISCV::Select_GPR_Using_CC_Imm` to condition on line 17670 to avoid entering `EmitLoweredCascadedSelect` which was intended for FP.

https://github.com/llvm/llvm-project/pull/89719